BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT

Avalahalli, Doddaballapura main road, Bangalore-64

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

HARDWARE DESCRIPTION LANGUAGE LABORATORY

MANUAL: 15ECL58

Vision

Provide Quality Education in Electronics, Communication and Allied

Engineering fields to Serve as Valuable Resource for Industry and Society.

Mission

1. Impart Sound Theoretical Concepts and Practical Skills.

2. Promote Inter-disciplinary Research.
3. Inculcate Professional Ethics.

Laboratory Incharges

Suryakanth B and Jagannatha K. B

Asst. Professors

Laboratory Instructor
Shivamallu
Instructor
HDL LAB MANUAL 15ECL58

Course Outcomes

Students will :

CO1: Design and conduct experiments on combinational and sequential circuits using various
Modelling approaches of VHDL and Verilog.

CO2: Comprehend, write and reproduce the programs and results.

CO3: Debug, Execute and Download the bit stream file on FPGA using Xilinx ISE project
navigator tool.

CO4: Design FPGA based systems using HDL.

Programme Educational Objectives

Graduates of the programme will:

PEO1: Work as professionals in the area of Electronics and allied engineering fields

PEO2: Pursue higher studies and involve in the interdisciplinary research work

PEO3: Exhibit ethics, professional skills and leadership qualities in their profession.

Programme Specific Outcomes

Graduates will be able to:

PSO1: Apply mathematical foundations, electronic design principles in modeling and design of electronic
systems that demonstrates comprehension of the trade-off involved in design choices.
PSO2: Apply design and development principles in the realization of hardware and software systems of
varying complexity.

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Programme Outcomes
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization for the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, research literature, and analyse complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for
public health and safety, and cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: The problems that cannot be solved by

straightforward application of knowledge, theories and techniques applicable to the engineering
discipline, that may not have a unique solution.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools, including prediction and modeling to complex engineering activities,
with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal, and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with t h e society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of t h e

engineering and management principles and apply these to one‟s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

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CO – PO – PSO MAPPING

CO PO1 PO2 PO3 PO4 PO PO6 PO PO PO9 PO10 PO11 PO12 PSO1 PSO2
5 7 8
CO1 3 3 1 3 3 1 3 2 1 3
CO2 3 3 1 3 3 1 3 2 1 3
CO3 3 3 1 3 3 1 3 2 1 3
CO4 3 3 1 3 3 2 3 2 2 1 3

COURSE: HDL LABORATORY CODE:10ECL58

COURSE OBJECTIVES - As part of this course, students:

1. Apply the concepts of basic combinational logic circuits, sequential circuit elements, and logic in
the laboratory setting.
2. Develop familiarity and confidence with designing, building and testing digital circuits, including the
use of CAD tools like Xilinx ISE Project navigator.
3. Develop team-building skills and enhance technical knowledge through both written assignments and
design projects

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CONTENTS
Sl. NO Title Page No
1 Syllabus 6

2 Cycles of Experiments 8

3 Overview of HDL lab 9

4 Introduction to FPGA 21

4 PART A - Combinational & Sequential Circuits 28

Programs
5 PART B -Interfacing Programs 57

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1. SYLLABUS
Subject code: 15ECL58 IA marks: 20
No. of practical Hrs. /week: 03 Exam hours: 03
Total no. of practical Hrs. 42 Exam marks: 80.
…………………………………………………………………………
(ACCORDING TO VTU SYLLABUS)
PART – A

PROGRAMMING

1.Write Verilog code to realize all the gates.

2.Write a Verilog program for the following combinational designs

a). 2 to 4 decoder
b). 8 to 3 (encoder without priority & with priority)
c). 8 to 1 multiplexer
d). 4 bit binary to gray converter
e). Multiplexer, de-multiplexer, comparator.

3. Write a HDL code to describe the functions of a full adder using three modeling styles.

4. Write a model for 32 bit ALU using the schematic diagram shown below A(31:0)

• ALU should use the combinational logic to calculate an output based on the four
bit op-code input.
• ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
• ALU should decode the 4 bit op-code according to the given in example below.

5. Develop the Verilog code for the following flip-flops SR, D, JK & T.

6. Design 4 bit binary, BCD counters (Synchronous reset and asynchronous reset) and “any
sequence” counters Using Verilog code.

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PART - B

INTERFACING (at least four of the following must be covered using

VHDL/Verilog)
1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven segment display.

3. Write HDL code to control speed, direction of DC and stepper motor.

4. Write HDL code to accept 8 channel analog signal, Temperature sensors and display the data on
LC panel or seven segment display

5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC
change the frequency and amplitude.

6. Write HDL code to simulate Elevator operation

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CYCLES OF EXPERIMENTS:

CYCLE EXPERIMENTS
1 1. Logic gates
2. Half adder
3. Full adder-3 Descriptions
4. Gray to binary Conversion

2 1. 2 to 4 decoder
2. 8 to 3 (encoder without priority & with priority)
3. 8 to 1 Multiplexer
4. Comparator
5. ALU

3 1. SR, D, JK & T Flip flop

2. 4-bit Binary counter
3. BCD counters
4. Mod –n Counter
(Synchronous reset and asynchronous reset) and “any sequence” counters

4 1. Stepper Motor
2. DC Motor
3. Seven segment Display
4. Elevator
5. DAC

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2. OVERVIEW OF HDL LAB

2.1 HDL
In electronics, a hardware description language or HDL is any language from a class of
Computer languages for formal description of electronic circuits. It can describe the circuit's
operation, its design and organization, and tests to verify its operation by means of simulation
HDLs are standard text-based expressions of the spatial, temporal structure and behavior of
electronic systems. In contrast to a software programming language, HDL syntax, semantics
include explicit notations for expressing time and concurrency, which are the attributes of
hardware. Languages whose only characteristic is to express circuit connectivity between a
hierarchies of blocks are properly classified as netlist languages.
HDLs are used to write executable specifications of some piece of hardware. A simulation
program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the
ability to model a piece of hardware before it is created physically. It is this execute ability
that gives HDLs the illusion of being programming languages. Simulators capable of supporting
discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.
It is certainly possible to represent hardware semantics using traditional programming languages
such as C++, although to function such programs must be augmented with extensive and
unwieldy class libraries. Primarily, however, software programming languages function as a
hardware description language
Using the proper subset of virtually any language, a software program called a synthesizer
can infer hardware logic operations from the language statements and produce an equivalent
netlist of generic hardware primitives to implement the specified behavior. This typically
requires the synthesizer to ignore the expression of any timing constructs in the text.

The two most widely-used and well-supported HDL varieties used in industry are
 VHDL (VHSIC HDL)
 Verilog

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2.2 VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is
commonly used as a design-entry language for field-programmable gate arrays and application-
specific integrated circuits in electronic design automation of digital circuits.
VHDL is a fairly general-purpose language, and it doesn‟t require a simulator on which to run
the code. There are a lot of VHDL compilers, which build executable binaries. It can read and
write files on the host computer, so a VHDL program can be written that generates another
VHDL program to be incorporated in the design being developed. Because of this general-
purpose nature, it is possible to use VHDL to write a test bench that verifies with the user,
and compares results with those expected. This is similar to the capabilities of the Verilog
language
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as
Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the
generated schematic can be verified using simulation software (such as ModelSim) which
shows the waveforms of inputs and outputs of the circuit after generating the appropriate
test bench. To generate an appropriate test bench for a particular circuit or VHDL code,
the inputs have to be defined correctly. For example, for clock input, a loop process or an
iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). When a VHDL model is
translated into the "gates and wires" that are mapped onto a programmable logic device such
as a CPLD or FPGA, then it is the actual hardware being configured, rather than the
VHDL code being "executed" as if on some form of a processor chip.
Both VHDL and Verilog emerged as the dominant HDLs in the electronics industry while
older and less-capable HDLs gradually disappeared from use. But VHDL and Verilog share
many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit
simulation. Neither possesses language constructs to describe recursively-generated logic
structures

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2.3 Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed -
signal circuits at various levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming
language so that it would be familiar to engineers and readily accepted. The language is case-
sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"
and "while", are similar. The formatting mechanism in the printing routines and language
operators and their precedence are also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces
to define a block of code. The concept of time, so important to a HDL won't be found in C The
language differs from a conventional programming language in that the execution of statements
is not strictly sequential. A Verilog design consists of a hierarchy of modules are defined
with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires
and registers. Concurrent and sequential statements define the behavior of the module by
defining the relationships between the ports, wires, and registers Sequential statements are
placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel,
qualifying Verilog as a Dataflow language. A module can also contain one or more instances
of another module to define sub-behavior
A subset of statements in the language is synthesizable. If the modules in a design contains a
netlist that describes the basic components and connections to be implemented in hardware only
synthesizable statements, software can be used to transform or synthesize the design into the net
list may then be transformed into, for example, a form describing the standard cells of an
integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).

Describing a design
In VHDL an entity is used to describe a hardware module
An entity can be described using,
1. Entity declaration
2. Architecture.

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1. Entity declaration
It defines the names, input output signals and modes of a hardware module
Syntax
Entity entity _ name is
port declaration
end entity name

An entity declaration should start with “entity” and ends with “end” keywords. Ports are
interfaces through which an entity can communicate with its environment. Each port must have a
name, direction and a type. An entity may have no port declaration also. The direction will be
input, output or inout.

2. Architecture:
It describes the internal description of design or it tells what is there inside design
each entity has at least one architecture and an entity can have many architectures.
Architecture can be described using structural, dataflow, behavioral or mixed style.

Syntax:
architecture architecture_name of entity_name is
architecture_declarative_part;
begin
statements;
end architecture_name;

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Here we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the begin and end keyword. Architecture declarative part
may contain variables, constants, or component declaration.
The internal working of an entity can be defined using different modeling styles inside
architecture body. They are

 Dataflow modeling
 Behavioral modeling
 Structural modeling.

Structure of an entity:

 Dataflow modeling
In this style of modeling, the internal working of an entity can be implemented using
concurrent signal assignment.
Consider a half adder as an example which is having one XOR gate and a AND gate as shown
below

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Program

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called
STD_ULOGIC. Use is a keyword, which imports all the declarations from this package. The
architecture body consists of concurrent signal assignments, which describes the functionality of
the design. Whenever there is a change in RHS, the expression is evaluated and the value is
assigned to LHS.

Behavioral modeling:
In this style of modeling, the internal working of an entity can be implemented using set of
statements.
It contains:
Process statements
Sequential statements
Signal assignment statements

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Process statement is the primary mechanism used to model the behavior of an entity it
contains sequential statements, variable assignment (:=) statements or signal assignment
(<=) statements etc. It may or may not contain sensitivity list. If there is an event occurs on any
of the signals in the sensitivity list, the statements within the process are executed. Inside the
process the execution of statements will be sequential and if one entity is having two
processes the execution of these processes will be concurrent. At the end it waits for another
event to occur.

Here whenever there is a change in the value of A OR B the process statements are executed.
Structural modeling
The implementation of an entity is done through set of interconnected components. It
contains
Signal declaration.
Component instances
Port maps.
Wait statements.

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Component declaration:
Syntax:
Component Component_name
List_of_interface ports;
end component component_ name;
Before instantiating the component it should be declared using component declaration as
shown above. Component declaration declares the name of the entity and interface of a
component.

Consider the example of full adder using 2 half adder and 1 OR gate.

Schematic Diagram of full adder

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The program written for half adder in dataflow modeling is instantiated as shown above.
HA is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal
connections of the component which are declared using the keyword signal. Port map is used to
connect different components as well as connect components to ports of the entity.

Component instantiation is done as follows.

Component_label: component_name port map (signal_list);

Signal list is the architecture signals which will be connected to component ports. This can be
done in different ways. What is declared above is positional binding. One more type is the named
binding.
The above can be written as,
HA1: ha port map (A => A, B => B, S => S1, C => C1);
HA2: ha port map (A => S1, B => Cin, S=> SUM, C => C2);

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2.4 Design using HDL

The vast majority of modern digital circuit design revolves around an HDL
description of the desired circuit, device, or subsystem
Most designs begin as a written set of requirements or a high-level architectural diagram.
The process of writing the HDL description is highly dependent on the designer's diagram.
The process of writing the HDL description is highly dependent on the designer's
background and the circuit's nature. The HDL is merely the 'capture language'–often begin
with a high-level algorithmic description such as MATLAB or a C++ mathematical model
Control and decision structures are often prototyped in flowchart applications, or entered in a
state-diagram editor. Designers even use scripting languages (such as PERL) to automatically
generate repetitive circuit structures in the HDL language. Advanced text editors (such as
PERL) to automatically generate repetitive circuit structures in the HDL language. Advanced
text editors (such as Emacs) offer editor templates for automatic indentation, syntax-
dependent coloration, and macro-based expansion of entity/architecture/signal declaration.
As the design's implementation is fleshed out, the HDL code invariably must undergo code
review, or auditing. In preparation for synthesis, the HDL description is subject to an array
of automated checkers. The checkers enforce standardized code guidelines, identifying
ambiguous code construct before they can cause misinterpretation by downstream synthesis, and
check for common logical coding errors, such as dangling ports or shorted outputs.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis
tool has mapped the HDL description into a gate net list, this net list is passed off to the back -
end stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-
cell), HDLs may or may not play a significant role in the back-end flow. In general, as the
design flow progresses toward a physically realizable form, the design database becomes
progressively more laden with technology-specific information, which cannot be becomes
progressively more laden with technology-specific information, which cannot be stored in a
generic HDL-description. Finally, a silicon chip is manufactured in a fab.

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2.5 Simulating and debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. Simulation allows a
HDL description of a design (called a model) to pass design verification, an important
milestone that validates the design's intended function (specification) against the code
implementation in the HDL description. It also permits architectural exploration. The engineer
can experiment with design choices by writing multiple variations of a base design, then
comparing their behavior in simulation. Thus, simulation is critical for successful HDL design
To simulate an HDL model, an engineer writes a top-level simulation environment (called
a test bench). At minimum, a test bench contains an instantiation of the model (called the
device under test or DUT), pin/signal declarations for the model's I/O, and a clock
waveform. An HDL simulator–the program that executes the test bench–maintains the
simulator clock, which is the master reference for all events in the test bench simulation
Events occur only at the instants dictated by the test bench HDL, or in reaction to
stimulus and triggering events.

Design verification is often the most time-consuming portion of the design process, due to the
disconnect between a device's functional specification, the designer's interpretation of the
specification, and the imprecision of the HDL language. The majority of the initial test/debug
cycle is conducted in the HDL simulator environment, as the early stage of the design is subject
to frequent and major circuit changes. An HDL description can also be prototyped and tested in
hardware–programmable logic devices are often used for this purpose. Hardware prototyping is
comparatively more expensive than HDL simulation, but offers a real-world view of the design.
Prototyping is the best way to check interfacing against other hardware devices, and
hardware prototypes, even those running on slow FPGAs, offer much faster simulation times
than pure HDL simulation.

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2.6. Requirements & Procedure

Requirements:
1. HDL software with front-end (Design entry, synthesis, simulation implementation and
programming)
2. FPGA kit with minimum 400,000 gate density

Procedure:
Software part
1. Click on the Project navigator icon on the desktop of your PC. Write the vhdl code, check
syntax and perform the functional simulation using ISE Simulator.
2. Open a new UCF file and lock the pins of the design with FPGA I/O pins.
3. Implement the design by double clicking on the implementation tool selection
4. Check the implementation reports.
5. Create programming file.

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3. INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY)

FPGA contains a two dimensional arrays of logic blocks and interconnections between logic
blocks. Both the logic blocks and interconnects are programmable. Logic blocks are programmed
to implement a desired function and the interconnects are programmed using the switch boxes to
connect the logic blocks.
To implement a complex design (CPU for instance), the design is divided into small sub
functions and each sub function is implemented using one logic block. All the sub functions
implemented in logic blocks must be connected and this is done by programming the
interconnects.

3.1 INTERNAL STRUCTURE OF AN FPGA

FPGAs, alternative to the custom ICs, can be used to implement an entire System On one Chip
(SOC). The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to
implement a design and this is done after the FPGA is manufactured. This brings the name
“Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when produced in
bulk amounts. But FPGAs are easy to implement within a short time with the help of Computer
Aided Designing (CAD) tools.
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3.2 XILINX FPGA

Xilinx logic block consists of one Look Up Table (LUT) and one FlipFlop. An LUT is used to
implement number of different functionality. The input lines to the logic block go into the LUT
and enable it. The output of the LUT gives the result of the logic function that it implements and
the output of logic block is registered or unregistered output from the LUT.

4-INPUT LUT BASED IMPLEMENTATION OF LOGIC BLOCK.

Xilinx LUT

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FPGA/ASIC Design Flow Overview

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The ISE (Integrated Synthesis Environment) design flow comprises the following steps:

1. Design Entry
Create an ISE project as follows:
1. Create a project.
2. Create files and add them to your project, including a user constraints (UCF) file.
3. Add any existing files to your project.

Functional Verification
You can verify the functionality of your design at different points in the design flow as follows:

 Before synthesis, run behavioral simulation (also known as RTL simulation).

2. Design Synthesis
Synthesize your design.

3. Design Implementation
Implement your design as follows:

1. Implement your design, which includes the following steps:

o Translate
o Map
o Place and Route

4. Xilinx Device Programming

Program your Xilinx device as follows:

1. Create a programming file (BIT) to program your FPGA.

2. Generate a PROM or ACE file for debugging or to download to your device. Optionally,
create a JTAG file.
3. Use iMPACT to program the device with a programming cable.

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3.2 PIN SHEET OF XC3S400-5TQ144

FRC1 FRC2 FRC3
1 74 IO 1 84 IO 1 100 IO

2 76 IO 2 85 IO 2 102 IO

3 77 IO 3 86 IO 3

4 79 IO 4 87 IO 4 103 IO

5 78 IO 5 89 IO 5 105 IO

6 82 IO 6 90 IO 6 107 IO

7 80 IO 7 92 IO 7 108 IO

8 83 IO 8 96 IO 8 113 IO

9 VCC POWER 9 VCC POWER 9 VCC POWER

10 GND SUPPLY 10 GND SUPPLY 10 GND SUPPLY

FRC4 FRC6 FRC7

1 112 IO 1 28 IO 1 57 IO

2 116 IO 2 31 IO 2 59 IO

3 119 IO 3 33 IO 3 63 IO

4 118 IO 4 44 IO 4 69 IO

5 123 IO 5 46 IO 5 68 IO

6 131 IO 6 47 IO 6 73 IO

7 130 IO 7 50 IO 7 70 IO

8 137 IO 8 51 IO 8 20 IO

9 VCC POWER 9 VCC POWER 9 VCC POWER

10 GND SUPPLY 10 GND SUPPLY 10 GND SUPPLY

FRC5 FRC8 FRC10

1 1 IO 1 93 IO 1 60 IO

2 12 IO 2 95 IO 2 56 IO

3 13 IO 3 97 IO 3 41 IO

4 14 IO 4 98 IO 4 40 IO

5 15 IO 5 99 IO 5 36 IO

6 17 IO 6 194 IO 6 35 IO

7 18 IO 7 IO 7 32 IO

8 21 IO 8 122 IO 8 10 IO

9 23 IO 9 129 IO 9 11 IO

10 24 IO 10 132 IO 10 8 IO

11 26 IO 11 135 IO 11 7 IO

12 27 IO 12 140 IO 12 6 IO

13 5 13 5 13 5

14 -5 14 -5 14 -5

15 VCC 15 VCC 15 VCC

16 GND SUPPLY 16 GND SUPPLY 16 GND SUPPLY

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FRC9

IO

IO

IO

141 IO

NA IO

NA IO

NA IO

NA IO

VCC
POWER
GND SUPPLY

Clk 52

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PART – A
PROGRAMS

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EXPERIMENT NO. 1
AIM: WRITE HDL CODE TO REALIZE ALL LOGIC GATES

A logic gate performs a logical operation on one or more logic inputs and produces a
single logic output. The logic normally performed is Boolean logic and is most commonly
found in digital circuits

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VERILOG CODE

module allgate ( a, b, yand,yor,ynot,ynand,ynor,yxor,yxnor );

input a,b;
output yand, yor, ynot, ynand, ynor, yxor, yxnor;
assign yand = a & b; // AND Operation
assign yor = a | b; // OR Operation
assign ynot = ~a ; // NOT Operation
assign ynand = ~(a & b); // NAND Operation
assign ynor = ~(a | b); //NOR Operation
assign yxor = a ^ b; //XOR Operation
assign yxnor =~(a^b); //XNOR Operation
endmodule // END of the module

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EXPERIMENT NO.2
AIM: Write HDL codes for the following combinational circuits.

2 a) 2 TO 4 DECODER RTL SCHEMATIC

Truth Table
EN Din(1) Din(0) Dout(3) Dout(2) Dout(1) Dout(0)
1 x x 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

VERILOG CODE

module dec2_4 (en,Din,Dout);

input en;
input [ 1 : 0 ] Din;
output [ 3 : 0 ] Dout;
reg [ 3 : 0 ] Dout;
always@(en,Din)
begin
if(en = = 1) //Active high enable
begin
Dout = 4'b0000; // Initializing Dout to 0000
end
else
begin
case (Din)
2'b00:Dout = 4'b0001;
2'b01:Dout = 4'b0010;
2'b10:Dout = 4'b0100;
2'b11:Dout = 4'b1000;
endcase
end
end
endmodule

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2 b) 8 TO 3 ENCODER WITHOUT PRIORITY

RTL Schematic

Truth Table
INPUTS OUTPUTS
en Din(7) Din(6) Din(5) Din(4) Din(3) Din(2) Din(1) Din(0) Dout(0) Dout(1) Dout(2)
1 x x x x x x x X z z z
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 0 0 0 0

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VERILOG CODE
module WPencode(en,Din,Dout);
input en;
input [ 7 : 0 ] Din;
output [ 2 : 0 ] Dout;
reg [ 2 : 0 ] Dout;
always@(en,Din)
begin
if(en == 1)
begin
Dout = 3‟bZZZ;
end
else
begin
case (Din)
8‟b00000001:Dout = 3‟b000;
8‟b00000010:Dout = 3‟b001;
8‟b00000100:Dout = 3‟b010;
8‟b00001000:Dout = 3‟b011;
8‟b00010000:Dout = 3‟b100;
8‟b00100000:Dout = 3‟b101;
8‟b01000000:Dout = 3‟b110;
8‟b01000000:Dout = 3‟b111;
endcase
end
end
endmodule

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2c) 8 TO 3 ENCODER WITH PRIORITY

RTL Schematic

Truth Table

INPUTS OUTPUTS
en Din(7) Din(6) Din(5) Din(4) Din(3) Din(2) Din(1) Din(0) Dout(0) Dout(1) Dout(2)
1 x x x x x x x x z z z
0 x x x x x x x 1 1 1 1
0 x x x x x x 1 0 1 1 0
0 x x x x x 1 0 0 1 0 1
0 x x x x 1 0 0 0 1 0 0
0 x x x 1 0 0 0 0 0 1 1
0 x x 1 0 0 0 0 0 0 1 0
0 x 1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 0 0 0 0

VERILOG CODE
module priori (en,Din,Dout);
input en;
input [ 7 : 0 ] Din;
output [ 2 : 0 ] Dout;
reg [ 2 : 0 ] Dout;
always@(en,Din)
begin
if(en == 1) // Active high enable
begin
Dout = 3'bZZZ; // Initializing Dout to high Impedance
end
else
begin
casex(Din)
8'b00000001 :Dout = 3'b000;
8'b0000001X :Dout = 3'b001;
8'b000001XX :Dout = 3'b010;

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8'b00001XXX :Dout = 3'b011;

8'b0001XXXX :Dout = 3'b100;
8'b001XXXXX :Dout = 3'b101;
8'b01XXXXXX :Dout = 3'b110;
8'b1XXXXXXX :Dout = 3'b111;
endcase
end
end
endmodule

Open ended Experiment

Design a 3bit priority encoder. The input I is 3-bit and the output P is 3-bit.
I (0) when high, has the highest priority, followed by I (1) and I (2).The output P
for highest Priority to lowest is 0, 1 and 2 (decimal). Respectively Construct the
truth table, minimize and write both VHDL and Verilog codes.

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2. d) 8 TO 1 MULTIPLEXER

Truth Table:

S(2) S(1) S(0)

0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
1 1 0 I(6)
1 1 1 I(7)

VERILOG CODE

module mux8_1(S,I,Y);
input [2:0]S;
input[7:0];
output Y;
reg Y;
always@(S,I)
begin
case(S)
3'b000:Y=I[0];
3'b001:Y=I[1];
3'b010:Y=I[2];
3'b011:Y=I[3];
3'b100:Y=I[4];
3'b101:Y=I[5];
3'b110:Y=I[6];
3'b111:Y=I[7];
endcase
end
endmodule

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2. e) 4-BIT BINARY TO GRAY CONVERTER

RTL Schematic

VERILOG CODE

module bin2gray(b,g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule

Open ended Experiment

Design a 4-bit parity generator .The output is 0 for even parity and 1 for odd parity
Write both the VHDL and Verilog codes

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2 f) 4-BIT COMPARATOR

Truth Table

Inputs Comparator O/P

a agtb aeqb altb
1000 1000 0 1 0
0111 1000 0 0 1
RTL Schematic 1000 0111 1 0 0

VERILOG CODE

module comp(a,b,aeqb,agtb,altb);
input [3:0] a,b;
output aeqb,agtb,altb;
reg aeqb,agtb,altb;
always @(a ,b)
begin
aeqb=0; agtb=0; altb=0;
if(a==b) //checking for equality condition
aeqb=1;
else if (a>b) // checking greater than condition
agtb=1;
else
altb=1;
end
endmodule

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EXPERIMENT NO.3

AIM: Write HDL code to describe the functions of a full Adder Using three modeling
styles.

RTL Schematic

Truth Table

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DATA FLOW

VHDL CODE VERILOG CODE

library IEEE; module fulladder ( a, b, cin,sum,cout);
use IEEE.STD_LOGIC_1164.ALL; input a, b,cin;
use IEEE.STD_LOGIC_ARITH.ALL; output sum, cout;
use IEEE.STD_LOGIC_UNSIGNED.ALL; assign sum= a ^ b ^ cin;
assign cout= (a & b) | (b & cin) | (cin & a);
entity fulladder is endmodule
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end fulladr;

architecture data of fulladr is

begin
sum<=a xor b xor cin;
cout<= ( a and b) or ( b and cin) or ( cin and a);
end data;

BEHAVIORAL STYLE
VHDL CODE VERILOG CODE
library IEEE; module fulladd(a,b,cin,sum,cout);
use IEEE.STD_LOGIC_1164.ALL; input a,b,cin;
use IEEE.STD_LOGIC_ARITH.ALL; output sum,cout;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg sum,cout;
always@(a,b,cin)
entity fulladder_beh is begin
Port ( a,b,cin : in std_logic; sum,cout : out std_logic); case ({a,b,cin}) // Concatenating (a,b,cin)
end fulladder_beh; 3'b000:{cout,sum}=2'b00;
3'b001:{cout,sum}=2'b01;
architecture Behavioral of fulladder_beh is 3'b010:{cout,sum}=2'b01;
signal abcin:std_logic_vector(2 downto 0); 3'b011:{cout,sum}=2'b10;
begin 3'b100:{cout,sum}=2'b01;
abcin<=a&b&cin; -- Concatenating (a,b,cin) 3'b101:{cout,sum}=2'b10;
process( abcin) 3'b110:{cout,sum}=2'b10;
begin 3'b111:{cout,sum}=2'b11;
case abcin is endcase
when”000”=>sum<=‟0‟;cout<=‟0‟; end
when”001”=>sum<=‟1‟;cout<=‟0‟; endmodule
when”010”=>sum<=‟1‟;cout<=‟0‟;
when”011”=>sum<=‟0‟;cout<=‟1‟;
when”100”=>sum<=‟1‟;cout<=‟0‟;
when”101”=>sum<=‟0‟;cout<=‟1‟;
when”110”=>sum<=‟0‟;cout<=‟1‟;

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when”111”=>sum<=‟1‟;cout<=‟1‟
; when others=>null;
end case;
end process;
end Behavioral;

STRUCTURAL MODELLING
VHDL CODE VERILOG CODE
---HALF ADDER
library IEEE; //HALF ADDER
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; module ha(x,y,s,c);
use IEEE.STD_LOGIC_UNSIGNED.ALL; input x,y;
entity halfadd is output s,c;
Port ( x,y :in STD_LOGIC; assign s = x^y;
s,c : out STD_LOGIC); assign c = x & y;
end halfadd; endmodule

architecture Behavioral of halfadd is

begin //FULL ADDER
s <= x xor y; ---xor operation module fulladder(a,b,cin,sum,cout);
c <= x and y; ---and operation input a, b,cin;
end Behavioral; output sum, cout;
---FULL ADDER wire temp1,temp2,temp3;
library IEEE; ha L1(a,b,temp1,temp2); // L1 & L2 are modules
use IEEE.STD_LOGIC_1164.ALL; ha L2(temp1,cin,sum,temp3);
use IEEE.STD_LOGIC_ARITH.ALL; assign cout= temp2 | temp3; // or operation
use IEEE.STD_LOGIC_UNSIGNED.ALL; endmodule
entity fulladd is
Port ( A,B,Cin : in STD_LOGIC;
Sum,Cout : out STD_LOGIC);
end fulladd;

architecture Behavioral of fulladd is

component halfadd port(x,y:in std_logic; s,c:out
std_logic);
end component;
signal temp1,temp2,temp3:std_logic;
begin
l1:halfadd port map(A,B,temp1,temp2);
l2:halfadd port map(temp1,Cin,Sum,temp3);
Cout <=temp2 or temp3;
end behavioral;

end Behavioral;
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EXPERIMENT NO. 4

AIM: Write a model for 4/8/32 bit Arithmetic Logic Unit using the schematic
diagram shown below.

VERILOG CODE

module ALU ( a, b, opcode, y );

input [3:0]a, b;
input [2:0]opcode;
output [7:0]y;
reg [7:0]y;
always@( a, b,opcode)
begin
case (opcode)
3‟d0: y=a+b;
3‟d1: y=a-b;
3‟d2: y={4‟ d0, (a | b)};
3‟d3: y={4‟ d0, (a & b)};
3‟d4: y={4‟ d0, ~a};
3‟d5: y=a*b;
3‟d6: y={4‟ d0, ~(a & b)};
3‟d7: y={4‟ d0, (a ^ b)};
default: begin end
endcase
end
endmodule

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32 bit Arithmetic Logic Unit

VERILOG CODE

module alu32( a, b,en,cout,opcode,zout );

input [31:0] a,b;
output cout;
input[3:0] opcode;
output [31:0]zout;
reg [31:0]zout;
reg [32:0]temp;
reg cout;
always@( a, b, opcode)
begin
case(opcode)
4'b0001: temp = a + b;
4'b0010: temp = a - b;
4'b0011: temp[31:0]= ~a;
4'b0100: temp= a[15:0]* b[15:0];
4'b0101: temp[31:0]= a & b;
4'b0110: temp[31:0]= a | b;
4'b0111: temp[31:0]= ~(a & b);
4'b1000: temp[31:0]= a ^ b;
default : temp= 8'bZ;
endcase
zout=temp[31:0]; cout=temp[32];
temp[32]=0;
end
endmodule

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EXPERIMENT NO.5
AIM: Develop the HDL code for the following flip-flop: T, D, SR and JK.

5.1) T- FLIP FLOP

RTL Schematic Truth Table

CLK T Q Qb OPERATION
x Q Qb No Change
Q Qb No Change
Qb Q Toggle

VERILOG CODE FOR TEST

BENCH WAVEFORM
module tff(t,clk,q,qb);
input t,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
if(t==1)
q=~q;
else
qb=~q;
end
endmodule

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VERILOG CODE FOR

DOWNLOADING ONTO A
FPGA
module tff(t,clk,q,qb);
input t,clk;
output q,qb;
reg q=0,qb=1;
reg [24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always@(posedge clkd[21])
begin
if(t==1)
q=~q;
else
q=q;
qb=~q;
end
endmodule

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5.2) D-FLIP FLOP

RTL Schematic
Truth Table

CLK D Q Qb OPERATION
0 x Q Qb No change
1 0 0 1 Reset
1 1 1 0 Set

VERILOG CODE
module dff(d,clk,q,qb);
input d,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
q= d;
qb=~q;
end
endmodule

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5.3) SR FLIP – FLOP

RTL Schematic
Truth Table

CLK Q Qb
x x Q Qb

Not defined
Q Qb

VERILOG CODE
module sr(sr,clk,q,qb);
input clk;
input[1:0]sr;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bZ;
endcase
qb=~q;
end
endmodule

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5.4) JK-FLIP FLOP

RTL Schematic Truth Table

CLK Q Qb
x x Q Qb

Qb Q
Q Qb

VERILOG CODE FOR TEST

BENCH WAVEFORM

module jkff1(jk,clk,q,qb);
input clk;
output q,qb;
reg q=0,qb=1;
input [1:0]jk;

always@(posedge clk)
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

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VERILOG CODE FOR

DOWNLOADING ONTO A
FPGA
module jkff1(jk,clk,q,qb);
input clk;
output q,qb;
reg q=0,qb=1;
input [1:0]jk;

reg[24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always@(posedge clkd[21])
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

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EXPERIMENT-6

6.1) SYNCHRONOUS RESET COUNTER

RTL Schematic Clock Reset Current Next

State State
1 1 Truth xxx
Table 0000
1 0 0000 0001
1 0 0001 0010
1 0 0010 0011
1 0 0011 0100
1 0 0100 0101
1 0 0101 0110
1 0 0110 0111
1 0 0111 1000
1 0 1000 1001
1 0 1001 1010
1 0 1010 1011
1 0 1011 1100
1 0 1100 1101
1 0 1101 1110
1 0 1110 1111
0 x 1111 0000

VERILOG CODE
module syncnt(clk,reset,count);
input clk,reset;
output [3:0] count;
reg[3:0]count=4'b0000;
reg[24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always @(posedge clkd[20])
begin
if(reset==1)
count = 4'b0000;
else
count = count+1;
end
endmodule

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6.2 )ASYNCHRONOUS RESET COUNTER

RTL Schematic

VERILOG CODE
module asyncnt(clk,reset,count);
input clk,reset;
output [3:0] count;
reg[3:0]count=4'b0;
reg[24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always @(posedge clkd[20] or posedge reset)
begin
if(reset==1)
count = 4'b0000;
else
count = count+1;
end
endmodule

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6.3 Binary synchronous UP COUNTER

VERILOG CODE
module bin( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @ (posedge clk)
begin
if (rst)
count =4'd0;
else
count = count +4'd1;
end
endmodule

6.4 Binary synchronous down COUNTER

VERILOG CODE
module bin( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @ (posedge clk)
begin
if (rst)
count =4'd15;
else
count = count -4'd1;
end
endmodule

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6.5 Binary asynchronous UP COUNTER

VERILOG CODE
module async_bin1( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
count =4'd0;
else
count = count +4'd1;
end
endmodule

6.6 BCD Synchronous Reset Counter

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VERILOG CODE
module bin_sync( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
//reg [23:0] clkd;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bcd_out=bcd_out+4'd1;
else
bcd_out=4'd0;
end
endmodule

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6.7 Four Bit BCD Asynchronous Reset Counter

VERILOG CODE
module bcd_async( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
//reg [23:0] clkd;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk or posedge rst)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bcd_out=bcd_out+4'd1;
else
bcd_out=4'd0;
end
endmodule

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6.8 4 Bit 3 to 9 sequence Counter

VERILOG CODE
module seqcnt( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
//reg [23:0] clkd;
initial
begin
count=4'd0;
end
always @ (posedge clk or posedge rst)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
count=4'd3;
else if(count<4'd9)
count=count+4'd1;
else
count=4'd3;
end
endmodule

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HDL LAB MANUAL 15ECL58

PART- B
INTERFACING
PROGRAMS

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1. Write HDL code to generate different waveforms (saw tooth, sine wave,
square, triangle, ramp etc.) using DAC change the frequency and
amplitude.
a)DAC-SQUARE WAVE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;

architecture Behavioral of squarewg is signal

temp:std_logic_vector(3 downto 0); signal
cnt:std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

process(temp(3))
begin
if rst='1' then
cnt<="00000000";
elsif rising_edge (temp(3)) then if
cnt< 255 and en='0' then
cnt<=cnt+1; en<='0';
dac<="00000000";
elsif cnt=0 then
en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process; end
Behavioral;

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NET "clk" LOC = "p52" ;

NET "dac<0>" LOC = "p21" ;
NET "dac<1>" LOC = "p18" ;
NET "dac<2>" LOC ="p17" ;
NET "dac<3>" LOC ="p15";
NET "dac<4>" LOC ="p14" ;
NET "dac<5>" LOC ="p13" ;
NET "dac<6>" LOC ="p12";
NET "dac<7>" LOC ="p1" ;
NET "rst" LOC ="p74" ;

b)DAC-TRIANGLE WAVE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;

architecture Behavioral of triangwg is

signal temp: std_logic_vector( 3 downto 0);
signal cnt: std_logic_vector(0 to 8);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+1;
end if;
end process;
process( temp(3))
begin
if rst='1' then
cnt<="000000000";
elsif rising_edge(temp(3)) then
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HDL LAB MANUAL 15ECL58

cnt<=cnt+1;
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<= not(cnt( 1 to 8));
end if;
end if;
end process;
end Behavioral;

NET "clk" LOC = "p52" ;

NET "dac<0>" LOC = "p21" ;
NET "dac<1>" LOC = "p18" ;
NET "dac<2>" LOC ="p17" ;
NET "dac<3>" LOC ="p15";
NET "dac<4>" LOC ="p14" ;
NET "dac<5>" LOC ="p13" ;
NET "dac<6>" LOC ="p12";
NET "dac<7>" LOC ="p1" ;
NET "rst" LOC ="p74" ;

Count (1 to 8) Count(0) Operation

0 0000 000 0 Compliment and decrement
0 0000 000 1 Increment from 0 to 254
0 0000 001 0 Compliment and decrement
0 0000 001 1 Increment
0 0000 010 0 Compliment and decrement
0 0000 010 1 Increment
0 0000 011 0 Compliment and decrement
0 0000 011 1 Increment
0 0000 100 0 Compliment and decrement
0 0000 100 1 Increment
: : :

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c)DAC-RAMP WAVE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;

architecture Behavioral of rampwg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then
cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;-------For falling RAMP cnt-1
end if;
end process;
dac<=cnt;
end Behavioral;

NET "clk" LOC = "p52" ;

NET "dac<0>" LOC = "p21" ;
NET "dac<1>" LOC = "p18" ;
NET "dac<2>" LOC ="p17" ;
NET "dac<3>" LOC ="p15";
NET "dac<4>" LOC ="p14" ;
NET "dac<5>" LOC ="p13" ;
NET "dac<6>" LOC ="p12";
NET "dac<7>" LOC ="p1" ;
NET "rst" LOC ="p74" ;

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HDL LAB MANUAL 15ECL58

FF+0000 0001=0000 0000 0000 0000-0000 0001=FF

d)DAC-SINE WAVE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sinewave is
Port (clk:in std_logic;
dout : out std_logic_vector(0 downto 7));
end sinewave;

architecture behavioral of sinewave is

signal a: integer range 1 to 1000000:=1;
signal b: integer range 0 to 49:=0;
signal r:std_logic:='1';
begin
process(clk,b,r)
type sine is array (0 to 49) of std_logic_vector (0 downto 7);
constant sinedata:sine:=(x"00", x"01", x"02",x"04", x"06", x"09", x"0C", x"0F",
x"14", x"18", x"1D", x"22",x"28", x"2E",x"34", x"3B",
x"42",x"49",x"50", x"58", x"5F", x"67", x"6F",x"77",
x"7F",x"87",x"8F",x"97",x"9F",x"A7",x"AE", x"B5",
x"BD",x"C3",x"CA",x"D0",x"D6",x"DC",x"E1",x"E6",
x"EB",x"FF",x"F3",x"F6",x"F8",x"FB", x"FC",x"FD",
x"FE",x"FF");

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begin
if (clk'event and clk='1')then
a<=a+1;
if (r='1') then
if (a=1) then
dout <=sinedata(b);
b<=b+1;
a<=1;
end if;

if (b=48) then
r<='0';
end if;
elsif (r='0') then
if (a=1) then
dout <= sinedata(b);
b<=b-1;
a<=1;
end if;
if (b=1) then
r<='1';
end if; end if; end if;
end process;
end behavioral;

NET "clk" LOC = "p52";

NET "dout<7>" LOC ="p1";
NET "dout<6>" LOC ="p12";
NET "dout<5>" LOC ="p13";
NET "dout<4>" LOC ="p14";
NET "dout<3>" LOC ="p15";
NET "dout<2>" LOC ="p17";
NET "dout<1>" LOC ="p18";
NET "dout<0>" LOC ="p21";

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HDL LAB MANUAL 15ECL58

Small „x‟ --- Hexadecimal number

Capital „X‟--- Unknown or don‟t care
θ = 180° / 50 intervals = 3.6° = Each interval
During Negative Quarter (1/4) cycle = 127.5-127.5 Sin (nθ ) 0≤ n ≤ 24

n=24 ---- 00 h
n=23 ---- 01 h
n=22 ---- 02 h
:
n=2 ---- 6F h
n=1 ---- 77 h
n=0 ---- 7F h corresponds to 127.5

During Positive Quarter (1/4) cycle = 127.5+127.5 Sin (nθ ) 1≤ n ≤ 25

n=1 ---- 87 h
n=2 ---- 8F h
n=3 ---- 97 h
:
n=24 ---- FE h
n=25 ---- FF h corresponds to 255

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HDL LAB MANUAL 15ECL58

2. SEVEN SEGMENT DISPLAY:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssg is
Port ( keyreturn : in STD_LOGIC_VECTOR (3 downto 0);
keyscan : buffer STD_LOGIC_VECTOR (3 downto 0):="1000";
segm : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
dis : out STD_LOGIC_VECTOR (6 downto 0):="0000000");
end ssg;

architecture Behavioral of ssg is

signal a:integer range 0 to 15:=0;
begin
process(clk)
begin
if(clk'event and clk='1')then
keyscan<=keyscan(0) & keyscan(3 downto 1);
if keyscan="0001" and keyreturn="0001" then a<=0;
elsif keyscan="0001" and keyreturn="0010" then a<=1;
elsif keyscan="0001" and keyreturn="0100" then a<=2;
elsif keyscan="0001" and keyreturn="1000" then a<=3;
elsif keyscan="0010" and keyreturn="0001" then a<=4;
elsif keyscan="0010" and keyreturn="0010" then a<=5;
elsif keyscan="0010" and keyreturn="0100" then a<=6;
elsif keyscan="0010" and keyreturn="1000" then a<=7;
elsif keyscan="0100" and keyreturn="0001" then a<=8;
elsif keyscan="0100" and keyreturn="0010" then a<=9;
elsif keyscan="0100" and keyreturn="0100" then a<=10;
elsif keyscan="0100" and keyreturn="1000" then a<=11;
elsif keyscan="1000" and keyreturn="0001" then a<=12;
elsif keyscan="1000" and keyreturn="0010" then a<=13;
elsif keyscan="1000" and keyreturn="0100" then a<=14;
elsif keyscan="1000" and keyreturn="1000" then a<=15;
end if;
end if;
end process;
process(a)
type sevseg is array (0 to 15 )of std_logic_vector(6 downto 0);
constant segdis:sevseg:= ("1111110","0110000","1101101","1111001",

"0110011","1011011","1011111","1110000",

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HDL LAB MANUAL 15ECL58

"1111111","1111011","1110111","0011111",

"1001110","0111101","1001111","1000111");

begin
dis<=segdis(a);
segm<="1110";---To activate one segment out of four segments
end process;
end Behavioral;

NET "clk" LOC = "p52" ;

NET "dis<0>" LOC = "p18" ;
NET "dis<1>" LOC = "p17" ;
NET "dis<2>" LOC = "p15" ;
NET "dis<3>" LOC = "p14" ;
NET "dis<4>" LOC = "p13" ;
NET "dis<5>" LOC = "p12" ;
NET "dis<6>" LOC = "p1" ;
NET "keyreturn<0>" LOC = "p112" ;
NET "keyreturn<1>" LOC = "p116" ;
NET "keyreturn<2>" LOC = "p119" ;
NET "keyreturn<3>" LOC = "p118" ;
NET "keyscan<0>" LOC = "p123" ;
NET "keyscan<1>" LOC = "p131" ;
NET "keyscan<2>" LOC = "p130" ;
NET "keyscan<3>" LOC = "p137" ;
NET "segm<0>" LOC = "p27" ;
NET "segm<1>" LOC = "p26" ;
NET "segm<2>" LOC = "p24" ;
NET "segm<3>" LOC = "p23" ;

If common cathode, a=b=c=d=e=f=g= 1

If common anode, a=b=c=d=e=f=g= 0
Keyscan / keyreturn 0111 1011 1101 1110
0111 0 1 2 3
1011 4 5 6 7
1101 8 9 A B
1110 C D E F

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HDL LAB MANUAL 15ECL58

Display a b c d e f g

0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1

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HDL LAB MANUAL 15ECL58

3. ELEVATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssg is
Port ( keyreturn : in STD_LOGIC_VECTOR (3 downto 0);
keyscan : buffer STD_LOGIC_VECTOR (3 downto 0):="1000";
segm : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
dis : out STD_LOGIC_VECTOR (6 downto 0):="0000000");
end ssg;

architecture Behavioral of ssg is

signal a,temp:integer range 0 to 15:=0;----initial content to be displayed after dumping
signal b:integer range 0 to 2000009;
begin
process(clk)
begin
if(clk'event and clk='1')then

keyscan<=keyscan(0) & keyscan(3 downto 1);

if keyscan="0001" and keyreturn="0001" then a<=0;

elsif keyscan="0001" and keyreturn="0010" then a<=1;
elsif keyscan="0001" and keyreturn="0100" then a<=2;
elsif keyscan="0001" and keyreturn="1000" then a<=3;
elsif keyscan="0010" and keyreturn="0001" then a<=4;
elsif keyscan="0010" and keyreturn="0010" then a<=5;
elsif keyscan="0010" and keyreturn="0100" then a<=6;
elsif keyscan="0010" and keyreturn="1000" then a<=7;
elsif keyscan="0100" and keyreturn="0001" then a<=8;
elsif keyscan="0100" and keyreturn="0010" then a<=9;
elsif keyscan="0100" and keyreturn="0100" then a<=10;
elsif keyscan="0100" and keyreturn="1000" then a<=11;
elsif keyscan="1000" and keyreturn="0001" then a<=12;
elsif keyscan="1000" and keyreturn="0010" then a<=13;
elsif keyscan="1000" and keyreturn="0100" then a<=14;
elsif keyscan="1000" and keyreturn="1000" then a<=15;
end if;
end if;
end process;

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HDL LAB MANUAL 15ECL58

Process(clk,a,temp)
begin
if(clk'event and clk='1')then
b<=b+1;
if(b=2000000)then ------Delay between one floor to next floor
if(temp<a) then -------a=current floor and temp= destination floor
temp<=temp+1 ;
b<=0;
elsif(temp/=a) then
temp<=temp-1 ;
b<=0;
end if;
end if;
end if;
end process;

process(temp) ---- when the key of destination floor is pressed process will be activated
type sevseg is array (0 to 15 )of std_logic_vector(6 downto 0);
constant segdis:sevseg:= ( "1111110","0110000","1101101","1111001",
"0110011","1011011","1011111","1110000",
"1111111","1111011","1110111","0011111",
"1001110","0111101","1001111","1000111");
begin
dis<=segdis(temp);
segm<="1110";
end process;
end Behavioral;

CURRENT FLOOR DESTINATION FLOOR INCREMENT/DECREMENT

0 5 increment from 0 to 5
1 4 increment from 1 to 4
2 6 increment from 2 to 6
3 8 increment from 3 to 8
4 A increment from 4 to A
5 7 increment from 5 to 7
6 E increment from 6 to E
7 6 decrement from 7 to 6
8 1 decrement from 8 to 1
9 3 decrement from 9 to 3
A 2 decrement from A to 2
B 8 decrement from B to 8
C 1 decrement from C to 1
D 5 decrement from D to 5
E 6 decrement from E to 6
F 3 decrement from F to 3

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HDL LAB MANUAL 15ECL58

4. DC MOTOR:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dcmotor is
Port ( clk : in STD_LOGIC;
reset,dir : in STD_LOGIC;
pwm : out STD_LOGIC_VECTOR (1 downto 0);
rly : out STD_LOGIC;
row : in STD_LOGIC_VECTOR (3 downto 0));
end dcmotor;

architecture Behavioral of dcmotor is

signal counter:STD_LOGIC_VECTOR (7 downto 0):="11111110";
signal div_reg:STD_LOGIC_VECTOR (16 downto 0);
signal dclk,ddclk,datain,tick:STD_LOGIC;
signal dcycle:integer range 0 to 255 ;
begin
process(clk,div_reg)
begin
if(clk'event and clk='1')then
div_reg<= div_reg+1;
end if;
end process;

ddclk<=div_reg(12);
tick<=row(0)and row(1)and row(2)and row(3);

process(tick)
begin
if falling_edge(tick)then
case row is
when "1110"=> dcycle<=255;---speed highest
when "1101"=> dcycle<=200;
when "1011"=> dcycle<=150;
when "0111"=> dcycle<=100;---speed lowest
when others=> dcycle<=100;
end case;
end if;
end process;

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HDL LAB MANUAL 15ECL58

process(ddclk,reset)
begin
if reset='0'then
counter<="00000000";
pwm<="01";
elsif(ddclk'event and ddclk='1')then
counter<=counter+1;
if(counter >=dcycle)then
pwm(1)<='0';
else
pwm(1)<='1';
end if;
end if;
end process;
rly<=dir;
end Behavioral;

NET "clk" LOC = "p52" ;

NET "dir" LOC = "p76" ;
NET "pwm<0>" LOC = "p4" ;
NET "pwm<1>" LOC = "p141" ;
NET "reset" LOC = "p74" ;
NET "rly" LOC = "p5" ;
NET "row<0>" LOC = "p69" ;
NET "row<1>" LOC = "p63" ;
NET "row<2>" LOC = "p59" ;
NET "row<3>" LOC = "p57" ;

Reset Direction/rly PWM operation

0 0 01 stop
1 1 11 Anticlockwise
1 0 11 clockwise

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HDL LAB MANUAL 15ECL58

5. STEPPER MOTOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;

architecture Behavioral of steppermt is

signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div+'1';
end if;
end process;
process(rst,clk_div(15)) -- speed is maximum at 15
begin
if rst='0' then shift_reg<="0001";
elsif rising_edge (clk_div(15)) then
if dir='1' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);----Clockwise
else
shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3);---Anticlockwise
end if;
end if;
end process;
dout<= shift_reg;

end Behavioral;

NET "clk" LOC ="p52";

NET "dir" LOC = "p85";
NET "rst" LOC = "p84";
NET "dout<0>" LOC = "p112";
NET "dout<1>" LOC = "p116";
NET "dout<2>" LOC = "p119";
NET "dout<3>" LOC = "p118";

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CLOCKWISE (DIR= ‘1’) ANTICLOCKWISE (DIR=’0’)

A B C D A B C D
1 0 0 0 0 0 1 0
0 1 0 0 0 1 0 0
0 0 1 0 1 0 0 0
0 0 0 1 0 0 0 1
ABCD ABCD ABCD ABCD….. CBAD CBAD CBAD CBAD…..

Reset Direction operation

0 X stop
1 1 clockwise
1 0 anticlockwise

When current is passed through the coil, the circular magnetic field is generated.

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