EC230 LOGIC CIRCUIT DESIGN LAB 10

Exp No: 2
Date :

ADDER AND SUBTRACTOR

AIM
To implement the half adder and full adder circuit using basic gates, universal gates and
verify their truth tables.
To implement the half subtractor and full subtractor using basic gates, universal gates
and verify their truth tables.

COMPONENTS AND EQUIPMENTS REQUIRED

IC-7486, IC-7400, IC-7402, IC-7408, Logic probe & IC Trainer kit.

THEORY

The simplest binary adder is called a half adder. Half adder has two inputs bits and two
output bits. One output bit is the sum and the other is carry. There are represented by S and C
respectively in the logic symbol.
A half adder has no provision to add a carry from the lower order bits when binary
numbers are added. When two input bits and a carry are to be added, the number of input bits
becomes three and the input combinations increases to eight. For this a full adder is used. Like
half adder it also as a sum bit and carry bit. The new carry generated is represented by C and
carry generated from the previous addition is represented by Cn-1.
A logic circuit for the binary subtraction between two single bit binary numbers is
known as half subtractor. It consists of two input bits and two output bits. One output bit is
borrow and other output bit is difference. They are represented by B′ and D respectively in
logic symbol. From the truth table it is clear that the difference output is zero if X=Y and 1 if X
≠ Y. The borrow output is 1 whenever X<Y. If X<Y then the subtraction is done by borrowing
1 from next higher order bit.
A logic circuit that can subtract three bits at a time is known as full subtractor. The
circuit has three inputs and two outputs. It handles only two bits at time and can be used for the
largest significant column of the subtractor problem. A full subtractor can however take care of
higher order column. The output of the full subtractor represented by D and B′, which is
difference and borrow respectively.
EC230 LOGIC CIRCUIT DESIGN LAB 11

TRUTH TABLE OF HALF ADDER

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

K-MAP FOR HALF ADDER

HALF ADDER USING BASIC GATES

A
S=A B
B

C = A.B

HALF ADDER USING NAND GATES

A S=A B
B

C = A.B
EC230 LOGIC CIRCUIT DESIGN LAB 12

HALF ADDER USING NOR GATES

A C = A.B
B
S=A B

TRUTH TABLE OF FULL ADDER

A B Cn-1 S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EC230 LOGIC CIRCUIT DESIGN LAB 13

FULL ADDER USING BASIC GATES

FULL ADDER USING NAND GATES

SUM
C

CARRY
EC230 LOGIC CIRCUIT DESIGN LAB 14

TRUTH TABLE OF HALF SUBTRACTOR

A B D B′
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

K-MAP FOR HALF SUBTRACTOR

HALF SUBTRACTOR USING BASIC GATES

B
D
A

B’
EC230 LOGIC CIRCUIT DESIGN LAB 15

HALF SUBTRACTOR USING NAND GATES

HALF SUBTACTOR USING NOR GATES

B’

A
D
B

TRUTH TABLE OF FULL SUBTRACTOR

A B C D B′
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
EC230 LOGIC CIRCUIT DESIGN LAB 16

K-MAP FOR FULL SUBTRACTOR

OR

FULL SUBTACTOR USING BASIC GATES

A
B D
C

B’
EC230 LOGIC CIRCUIT DESIGN LAB 17

FULL SUBTRACTOR USING NAND GATES

B D
F

C
B’

FULL SUBTRACTOR USING NOR GATES

B’
A

C
D

PROCEDURE

1. Verify whether all the components and wires are in good condition.
2. Setup the adder and subtractor circuit and feed the input combinations.
3. Observe the output corresponding input combinations and enter it in the truth table.

RESULT
The adder and subtractor circuit were implemented using basic gates, universal gates
and verified the truth tables.

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