Trap behaviours characterization of AlGaN/GaN high electron mobility transistors by

room-temperature transient capacitance measurement

Bin Dong, Jie Lin, Ning Wang, Ling-li Jiang, Zong-dai Liu, Xiaoyan Hu, Kai Cheng, and Hong-yu Yu

Citation: AIP Advances 6, 095021 (2016); doi: 10.1063/1.4963740

View online: http://dx.doi.org/10.1063/1.4963740
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 AIP ADVANCES 6, 095021 (2016)

Trap behaviours characterization of AlGaN/GaN high

electron mobility transistors by room-temperature
transient capacitance measurement
Bin Dong,1 Jie Lin,1 Ning Wang,1 Ling-li Jiang,1 Zong-dai Liu,1 Xiaoyan Hu,1
Kai Cheng,2 and Hong-yu Yu1,a
1 Department of Electrical and Electronic Engineering, Southern University of Science
and Technology, Shenzhen, 518055, China
2 Enkris Semiconductor Inc., NW-20v, Nanopolis Suzhou, 99 Jinji Avenue,

215123, Suzhou, China

(Received 12 July 2016; accepted 14 September 2016; published online 22 September 2016)

In this paper, the trap behaviours in AlGaN/GaN high electron mobility transis-
tors (HEMTs) are investigated using transient capacitance measurement. By mea-
suring the transient gate capacitance variance (∆C) with different pulse height,
the gate pulse induced trap behaviours in SiNX gate dielectric layer or at the
SiNX /AlGaN interface is revealed. Based on the results, a model on electron traps
in AlGaN/GaN HEMTs is proposed. The threshold voltage (Vth ) instability in
AlGaN/GaN HEMTs is believed to be correlated with the presence of these traps
in SiNX gate dielectric layer or at the SiNX /AlGaN interface. Furthermore, trap den-
sity before and after step-stress applied on drain electrode is quantitatively analyzed
based on ∆C measurement. © 2016 Author(s). All article content, except where oth-
erwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). [http://dx.doi.org/10.1063/1.4963740]

I. INTRODUCTION
AlGaN/GaN-based high electron mobility transistor (HEMT) is considered as a promising candi-
date for power device applications in the field of power grid, automobiles, wireless communication,
and etc. As compared with conventional Si-based power devices, owing to the material property
advantages of GaN (e.g. wider band gap energy of 3.45eV, lower specific on-resistance, larger crit-
ical electric field, excellent thermal stability etc.), AlGaN/GaN HEMTs can achieve higher current
density, lower switching energy loss, higher breakdown field and higher frequency.1–3 Recently GaN-
on-Si substrate attracts a lot of attention due to its low cost towards mass production.4–6 It is also
noted that the high-K dielectric application in AlGaN/GaN HEMTs have also been actively stud-
ied, like the high-K application in the field of thin film transistors.7,8 However, the reliability of
AlGaN/GaN HEMTs is still of a great concern.9 Some researchers have associated the major degra-
dation mechanisms in AlGaN/GaN HEMTs such as the current collapse,10 threshold voltage shift,11
and the increase of the gate/drain leakage current 12 with the deep level traps in the device.13 On the
other hand, a clear understanding between trap behaviours and device reliability is still highly desir-
able.14–20 It is reported that deep-level-transient-spectroscopy (DLTS) can assist in the quantitative
analysis of the deep level defects in AlGaN/GaN HEMTs, which requires a well-controlled tempera-
ture cabinet with a wide temperature scope (dozens of K to hundreds of K).21,22 In this work, we use
a room-temperature transient capacitance measurement to study the trap behaviours in AlGaN/GaN
HEMTs using 6-inches GaN-on-Si substrate. A possible model on the trapping mechanism is thus
proposed to explain the threshold voltage (Vth ) instability in AlGaN/GaN HEMTs based on our
measurement data. Furthermore, we provide a methodology for quantitative analysis on trap density

aAuthor to whom correspondence should be addressed. Electronic mail: yu.hy@sustc.edu.cn

2158-3226/2016/6(9)/095021/7 6, 095021-1 © Author(s) 2016

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 095021-2 Dong et al. AIP Advances 6, 095021 (2016)

variation of AlGaN/GaN HEMTs before and after step stress applied on drain electrode based on the
transient gate capacitance variance measurement.

II. EXPERIMENTS
Fig. 1 (a) shows a schematic of the AlGaN/GaN HEMTs used in this work. A 3.8 µm unintention-
ally doped GaN layer followed by a 22 nm Al0.22 Ga0.78 N barrier is grown on 6-inch Si substrate using
metal-organic chemical vapour deposition (MOCVD) to produce the GaN-on-Si wafer. A 2-DEG can
be formed at the AlGaN/GaN interface. The mobility and 2-DEG electron density are measured to
be 1900 cm2 /V s and 1.2×1013 cm2 respectively. A 35 nm SiNx layer is then deposited on the GaN-
on-Si wafer as the gate dielectric using low pressure chemical vapour deposition (LPCVD). The
multi-fingered gate width is 8.5 mm and the gate length is 2 µm. The gate-drain spacing (LGD ) is
15 µm, and the gate-source spacing (LGS ) is 2 µm. TiN/Ti/Al/Ti (20/20/120/20nm) stack are deposited
using sputter as Ohmic contact metal layer (source/drain region) in this device. The ohmic contact
is then formed by annealing in nitrogen ambient at the temperature 850 degree C for 30s by a rapid
thermal annealer. Fig. 1 (b) and (c) show the output characteristics and the transfer characteristics of
the pristine fabricated device. The Vth of device is measured as around -7.5 V. The maximum drain
current is ∼ 648 mA/mm at Vgs = 7 V. The breakdown voltage is up to 750V (measured at the drain
current as 0.1 mA/mm).
Room temperature transient capacitance measurement is used to study the trapping behaviours
in the device. Fig. 2 displays the experimental setup system. In this system, the source and drain
terminals are grounded. A cycle pulse is applied to the gate, and the corresponding transient gate
capacitance is measured using a Keithley 590 fast C-V analyzer. The pulse period is 30 ms, and the
width is 5 ms. In the measurement, when the pulse voltage reaches the peak value, the traps in the
AlGaN layer are filled with electrons from the conduction band. The gate capacitance also reaches
the peak value, as shown in Fig. 3 (a). The depletion region became wider with applied reverse
pulse voltage to the gate, which leads to the drop of the capacitance. With the electrons emitted
from the traps, the capacitance could slowly return back to the previous value at the steady state,
shown in Fig. 3 (b). Therefore, the filling and emptying traps process induces a gate capacitance
changing over time. By calculating the average of capacitance variance (∆C) in three pulse periods,
a ∆C ∼ t curve can be extracted. With increasing the pulse peak voltage on the gate from 1 V
to 7 V with a stable reverse voltage (-4V), a series of ∆C ∼ t curves are measured at the room
temperature. Each measurement is repeated for 3 times, the error bar scale is around 3-4%. Note
that all measurements are conducted in the dark environment since light irradiation could affect the
trap behaviours.

FIG. 1. (a) A schematic diagram of the AlGaN/GaN HEMT device fabricated in this work. (b) Output characteristics of the
device.(c) Transfer characteristics of the device.

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 095021-3 Dong et al. AIP Advances 6, 095021 (2016)

FIG. 2. Experimental setup system for transient capacitance measurement.

FIG. 3. The mechanism of pulse induced transient capacitance changing in AlGaN/GaN HEMTs.

III. RESULTS AND DISCUSSIONS

The ∆C∼t curves under various gate pulses are summarized in Fig. 4. We observed that ∆C
increases with Vpeak at beginning and then drops down when Vpeak is higher than 3 V. It is interesting
to note that when Vpeak is higher than 5 V, ∆C is reduced dramatically and even becomes negative.
The trend of ∆C under different conditions can be correlated with the trap behaviours in AlGaN/GaN
HEMTs. A possible model of trapping mechanism is proposed (see Fig. 5). When the pulse is
relatively small (e.g. Vpeak is set to 1 V only in Fig. 4), the pulse voltage can not attract enough free
electrons to fill up the deep level traps in the AlGaN/GaN HEMTs, as shown in Fig.5 (a). With the
pulse peak increasing, more deep level traps can be exposed. During a cycle pulse, more electrons
fill the extra defects,shown in Fig.5 (b). Therefore, ∆C starts to increasing with Vpeak (e.g. from
Vpeak = 1 V to Vpeak = 3 V in Fig. 4). However, the pre-existing electron traps in SiNX layer or at
SiNX /AlGaN interface will be activated with further increasing the gate pulse voltage, as shown in
Fig.5 (c). The effect becomes more remarkable after further increasing gate pulse voltage. It can be
seen that ∆C is reduced dramatically and even becomes negative (e.g. Vpeak increases to larger than 5 V
in Fig. 4).
Following the previous experiments, the device degradation induced by the gate pulse stress and
the drain electrical stress are also studied. With the pulse stress applied on the gate, it can be observed
in Fig 6 that the Vth of the AlGaN/GaN HEMTs is shifted to the positive direction In addition, Vth
increases rapidly at the early stage of stressing, then saturates gradually after 10 min. Based on the

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 095021-4 Dong et al. AIP Advances 6, 095021 (2016)

FIG. 4. The ∆C ∼ t curves when Vreverse is fixed as -4 V and Vpeak is changed from 1 V to 7 V. The period and duration of
all applied gate pulses are set as 30 ms and 5 ms respectively.

FIG. 5. (a) Small pulse cannot attract enough free electrons to fill up the deep level traps. (b) More traps are filled up and
emptied during the pulse with the pulse height increasing. (c) Further increase of the gate pulse actives the possible pre-existing
traps, and induces negative charged states.

FIG. 6. Vth variation of the AlGaN/GaN MIS-HEMT with a continued gate pulse. The period and pulse width of the applied
gate pulse cycles are 30 ms and 5 ms, respectively. The reverse voltage (Vreverse ) is 0V, and peak voltage (Vpeak ) of the pulse
is set as 7 V.

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 095021-5 Dong et al. AIP Advances 6, 095021 (2016)

possible model of electron traps in AlGaN/GaN HEMTs (see Fig. 5), it is believed that the shift of
threshold voltage can be partially attributed to the pre-existing electron traps in SiNX layer or at the
SiNX /AlGaN interface.
Electrical stress applied to the device could induce both temporary and permanent current collapse
because of electron traps in AlGaN/GaN HEMTs.24 The drain stress induced trap density changing
is studied based on the above-presented transient capacitance measurement. A step-stress (see Fig.7)
is applied to the drain electrode with a negative bias of -15 V on the gate (device is at off-state). The
transient capacitance characteristics before and after stressing are shown in Fig.7 (b). It can be seen
that the capacitance variance (∆C) increases after the drain step-stress. Based on the above-presented
trapping model, the increment of capacitance variance is believed to be correlated with the increment
of deep level defects concentration in AlGaN/GaN HEMTs. Since the applied stress bias on drain
could cause the accumulation of the deep level traps, more electrons can fill up the traps, and thus to
be emitted at the steady state. Therefore, the capacitance variance could increase after drain stress,
which is similar with the increment of capacitance variance when gate pulse increases from a small
value (e.g. from Vpeak = 1 V to Vpeak = 3 V in Fig. 4). To quantitatively analyse the traps behaviours,

FIG. 7. (a) The solid line indicates the step-stress applied to the drain terminal. (b) Transient capacitance characteristics of
AlGaN/GaN HEMT before and after the drain stress. The period and pulse width of the pulse are 30 ms and 5 ms respectively.
The reverse voltage (Vreverse) is -3V, and peak voltage (Vpeak ) of the pulse is set as 3 V.

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 095021-6 Dong et al. AIP Advances 6, 095021 (2016)

FIG. 8. The relation of 1/C 2 and V obtained on AlGaN/GaN HEMT before the stress at room temperature.

TABLE I. The change in transient capacitance and the corresponding trap density.

∆C Trap density

Before drain stress 0.92×10-11 F 1.404×1015 cm-3

After drain stress 1.12×10-11 F 1.709×1015 cm-3

the trap density is estimated based on the Equation (1).18

∆C NT
= (1)
C0 2ND
Where C 0 is the capacitance value of steady state, N T is the trap density and N D is the doping
concentration respectively.23 The transient change of capacitance ∆C is calculated from a time window
of 15ms. Before applied step-stress, the value of ∆C is 0.92×10-11 F. After applied step-stress, ∆C
increases to 1.12×10-11 F due to the step-stress induced extra traps. Doping concentration N D can be
calculated using the Equation (2):
1 2V
= (2)
C 2 εeND A2

Equation (2) indicates 1/C 2 is a linear function of the gate voltage V g near the value of threshold
voltage (∼ -7.7V), as shown in Fig. 8. The net doping concentration N D ∼ 9.081×1015 cm-3 can
be determined from the relation of 1/C 2 and V g . Then, according to Equation (1), Calculating the
trap density before and after electrical stress are 1.404×1015 cm-3 and 1.709×1015 cm-3 respectively.
These results match roughly with previous literatures.25–28 Deep level traps were induced in the
near-interface of SiNX /AlGaN during electrical stress. The results are summarized in Table I.

IV. CONCLUSION
In conclusion, the transient capacitance measurement is introduced to study the trap behaviours
in AlGaN/GaN HEMTs. By the transient capacitance measurement, the trap behavior mechanism is
proposed to explain threshold voltage instability of AlGaN/GaN HEMTs Furthermore, the change of
traps density before and after step-stress on drain electrode is quantitatively analyzed.

ACKNOWLEDGMENTS
This work is sponsored by the Key laboratories of third-generation semiconductor devices in
Shenzhen (Grant No. ZDSYS20140509142721434), the project of 2014-084 Key Technology Devel-
opment of Si based GaN power devices (Grant No. JSGG20140729145956266) and the project of
Energy-efficient Si based GaN power devices (Grant No. KQCX20140522151322946), the funda-
mental research project of science and technology plan of Shenzhen(JCYJ20140415162542983).

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 095021-7 Dong et al. AIP Advances 6, 095021 (2016)

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