Proyecto

Código Principal

library ieee;
use ieee. std_logic_1164.all;

entity lavadora is

PORT( encendido : in std_logic;

lleno : in std_logic;

tapa : in std_logic;

clock : in std_logic;

Llenaragua: out std_logic;

Vaciar : out std_logic;

veloci: out std_logic_vector(2 downto 0);

direc : out std_logic_vector(2 downto 0);

Alarma,x : out std_logic;

tiempou,tiempod : out std_logic_vector(3 downto 0);

estadol,ante : out std_logic_vector(2 downto 0);

relc,relm : out std_logic;

seg : out std_logic_vector(7 downto 0);

disp : out std_logic_vector(3 downto 0)

);

end lavadora;

architecture proceso of lavadora is

component maquina is

Port ( clock : in std_logic;

X : in std_logic;

clear : in std_logic;

estado : out std_logic_vector(2 downto 0);

 anterior : out std_logic_vector(2 downto 0)

);

end component;

component contadorvar is

Port ( clock : in STD_LOGIC;

cero : in std_logic;

finconteo : out std_logic;

estado : in STD_LOGIC_vector (2 downto 0);

contu : out STD_LOGIC_vector(3 downto 0);

contd : out std_logic_vector(3 downto 0)

);

end component;

component FFD is

PORT( D,CLOCK,pre,clea: in std_logic;

Q: out std_logic);

end component;

component num2let is

port

num: in std_logic_vector (2 downto 0);

segmentos: out std_logic_vector(7 downto 0));

end component;

component relojcontador is
 port(clk50mhz: IN STD_LOGIC;

clkOUT: INOUT STD_LOGIC);

end component;

component relojbarrido is

port(clk50mhz: IN STD_LOGIC;

clkOUT: INOUT STD_LOGIC);

end component;

component barrido is

port

numero7seg1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

numero7seg2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

numero7seg3: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

numero7seg4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

clk: IN STD_LOGIC;

segmentos: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

displays: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

end component;

component bcdto7 is

port (

numbcd : in std_logic_vector(3 downto 0); --BCD input

segmentos : out std_logic_vector(7 downto 0) -- 7 bit decoded output.

);

end component;
signal
finconteo,clear,cero,relojb,relojcon,relojmdeb,xmaquinadeb,memoria,buzzer,aux,aux2,xmaquina,
relojM,relojC,reiniciar : std_logic;

signal estado,anterior,q : std_logic_vector(2 downto 0);

signal contu,contd,tempu,tempd : std_logic_vector(3 downto 0);

signal contu7,contd7,velocidad,direccion: std_logic_vector(7 downto 0);

signal vel,dir : std_logic_vector(2 downto 0);

begin

maquinain:maquina

port map(

clock=>relojM,

X=>xmaquina,

clear=>reiniciar,

estado=>estado,

anterior=>anterior

);

contador:contadorvar

port map(

clock=>relojC,

cero=>relojM,

finconteo=>finconteo,

estado=>estado,

contu=>contu,

contd=>contd

);
reinicio:FFD

port map(

D=>(not(estado(0)) and estado(1) and estado(2) and (not(buzzer))),

CLOCK=>tapa,

pre=>'1',

clea=>'1',

q=>aux2

);

RelojCont: relojcontador

port map(

clk50mhz=>clock,

clkOUT=>relojcon

);

RelojBarr: relojbarrido

port map(

clk50mhz=>clock,

clkOUT=>relojb

);

Barrid: barrido

port map(

numero7seg1=>contu7,

numero7seg2=>contd7,

numero7seg3=>velocidad,

numero7seg4=>direccion,

clk=>relojb,

segmentos=>seg,
 displays=>disp

);

BCDto1: bcdto7

port map(

numbcd=>contu,

segmentos=>contu7

);

BCDto2: bcdto7

port map(

numbcd=>contd,

segmentos=>contd7

);

velo: num2let

port map(

num=>vel,

segmentos=>velocidad

);

dire: num2let

port map(

num=>dir,

segmentos=>direccion

);

Llenaragua<=(not(estado(2))and (not(estado(1))) and estado(0));

Vaciar <= (not(estado(2))and estado(1) and estado(0));

reiniciar<=aux2 or (not(encendido));

buzzer <=estado(2) and (estado(1)) and (not(estado(0))) and (not(tapa));

memoria <= ((((anterior(2))) and not(anterior(1)) and not(anterior(0)))) or (not(anterior(2)) and
(anterior(1)) and (anterior(0)) and not(estado(2))) or buzzer;

xmaquina<= (((encendido and (lleno and not(tapa))) or (finconteo)) and (not(memoria)));

relojM <=(not(relojcon) and (not(aux and not(finconteo))));

relojC <=(relojcon and (not(tapa)) and (aux and not(finconteo)));

--aux<='0';

with estado select aux<=

'1' when "001",

'1' when "010",

'1' when "011",

'1' when "100",

'1' when "101",

'0' when others;

--aux<=((not(estado(2)) and not(estado(1)) and estado(0)) or (not(estado(2)) and estado(1) and

not(estado(0))) or (not(estado(2)) and estado(1) and estado(0)) or (estado(2) and not(estado(1))
and not(q(0))) or (estado(2) and not(estado(1)) and estado(0)));

process(relojcon)

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(estado="010" or estado="100") then

vel<="010";

elsif(estado="101") then

vel<="001";

else

vel<="111";

end if;
 if(estado="010" and contu(1)='0') then

dir<="011";

elsif(estado="010" and contu(1)='1')then

dir<="000";

else

dir<="111";

end if;

end if;

end process;

estadol<=estado;

relc<=relojc;

relm<=relojm;

ante<=anterior;

x<=xmaquina;

veloci<=vel;

direc<=dir;

tiempou<=contu;

tiempod<=contd;

end;

Componente FFD

library ieee;

use ieee. std_logic_1164.all;

entity FFD is
PORT( D,CLOCK,pre,clea: in std_logic;
Q: out std_logic);
end FFD;
architecture behavioral of FFD is

begin

process(CLOCK)

begin

if(CLOCK='1' and CLOCK'EVENT) then

if pre ='0' then
Q<='1';
elsif clea ='0' then
Q <= '0';
else
Q <= D;
end if;
end if;

end process;
end behavioral;

Componente debouncer_top

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity debouncer_top is
port (
clk : in std_logic;
btn_in : in std_logic;
btn_out : out std_logic);
end debouncer_top;

architecture beh of debouncer_top is

constant CNT_SIZE : integer := 19;
signal btn_prev : std_logic := '0';
signal counter : std_logic_vector(CNT_SIZE downto 0) := (others => '0');

begin
process(clk)
begin
if (clk'event and clk='1') then
if (btn_prev xor btn_in) = '1' then
 counter <= (others => '0');
btn_prev <= btn_in;
elsif (counter(CNT_SIZE) = '0') then
counter <= counter + 1;
else
btn_out <= btn_prev;
end if;
end if;
end process;
end beh;

Componente ContadorVar
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity contadorvar is
Port ( clock : in STD_LOGIC;
cero : in std_logic;
finconteo : out std_logic;
estado : in STD_LOGIC_vector (2 downto 0);
contu : out STD_LOGIC_vector(3 downto 0);
contd : out std_logic_vector(3 downto 0)
);
end contadorvar;

architecture proceso of contadorvar is

component JK is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clock : in STD_LOGIC;
clear : in std_logic;
q : out STD_LOGIC;
noq : out STD_LOGIC
);
end component;

component Bin5toBCD is
PORT(
bin: in STD_LOGIC_VECTOR(4 downto 0);
bcd_u: out STD_LOGIC_VECTOR(3 downto 0);
bcd_d: out STD_LOGIC_VECTOR(3 downto 0);
bcd_c: out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal c : std_logic_vector(4 downto 0):="00000";
signal aux,aux2 :std_logic:='0';

begin

C1:JK
port map(
J=>'1',
K=>'1',
clock=>not(clock),
clear=>cero,
q=>c(0)
);

C2:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(0)),
clear=>cero,
q=>c(1)
);
C3:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(1)),
clear=>cero,
q=>c(2)
);
C4:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(2)),
clear=>cero,
q=>c(3)
);
C5:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(3)),
 clear=>cero,
q=>c(4)
);

BCD: Bin5toBCD
port map(
bin=>c,
bcd_u=>contu,
bcd_d=>contd
);

process(clock)
begin

if((estado="001" and c="00101")or(estado="010" and c="11010")or(estado="011" and

c="00100")or(estado="100" and c="01011")or(estado="101" and c="00110")) then
aux2<='1';
else
aux2<='0';
end if;
end process;

finconteo<=aux2;

end;

Componente Bin5toBCD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Bin5toBCD is
PORT(
bin: in STD_LOGIC_VECTOR(4 downto 0);
bcd_u: out STD_LOGIC_VECTOR(3 downto 0);
bcd_d: out STD_LOGIC_VECTOR(3 downto 0);
bcd_c: out STD_LOGIC_VECTOR(3 downto 0));
end Bin5toBCD;

architecture Behavioral of bin5tobcd is

begin
proceso_bcd: process(bin)
variable z: STD_LOGIC_VECTOR(16 downto 0);
begin
 -- Inicialización de datos en cero.
z := (others => '0');
-- Se realizan los primeros tres corrimientos.
z(7 downto 3) := bin;
for i in 0 to 1 loop
-- Unidades (4 bits).
if z(8 downto 5) > 4 then
z(8 downto 5) := z(8 downto 5) + 3;
end if;
-- Decenas (4 bits).
if z(12 downto 9) > 4 then
z(12 downto 9) := z(12 downto 9) + 3;
end if;
-- Centenas (3 bits).
if z(16 downto 13) > 4 then
z(16 downto 13) := z(16 downto 13) + 3;
end if;
-- Corrimiento a la izquierda.
z(16 downto 1) := z(15 downto 0);
end loop;
-- Pasando datos de variable Z, correspondiente a BCD.
bcd_u <= z(8 downto 5);
bcd_d <= z(12 downto 9);
bcd_c <= z(16 downto 13);
end process;
end Behavioral;

Componente bcdto7

library IEEE;
use ieee.std_logic_1164.all;

entity bcdto7 is
port
(
numBCD: in std_logic_vector (3 downto 0);
segmentos: out std_logic_vector(7 downto 0));

end bcdto7;

architecture arqui of bcdto7 is

begin
 with numBCD select

segmentos <= "00000011" when "0000",

"10011111" when "0001",
"00100101" when "0010",
"00001101" when "0011",
"10011001" when "0100",
"01001001" when "0101",
"11000001" when "0110",
"00011101" when "0111",
"00000001" when "1000",
"00001001" when "1001",
"11111111" when others;
end arqui;

Componente Barrido

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity barrido is
port
(
numero7seg1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg3: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk: IN STD_LOGIC;
segmentos: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
displays: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end barrido;

architecture behaviour of barrido is

signal cont: integer := 0;
begin

BarrDispl:process(clk)
begin

if falling_edge(clk) then
 if cont = 1 then
segmentos <= numero7seg1; -- Saco por Segm el numero1
displays <= "1110"; -- Prendo displays de Derecha a Izquierda.
-- Display Activo =
0L.
cont <= cont + 1; -- Actualizo Contador cnt

elsif cont = 3 then

segmentos <= numero7seg2; -- Saco por Segm el numero2
displays <= "1101"; -- Prendo 2do displays de Derecha a Izquierda.
-- Display Activo =
0L.
cont <= cont + 1; -- Actualizo Contador cnt

elsif cont <= 5 then

segmentos <= numero7seg3; -- Saco por Segm el numero2
displays <= "1011"; -- Prendo 2do displays de Derecha a Izquierda.
-- Display Activo =
0L.
cont <= cont + 1; -- Actualizo Contador cnt

elsif cont = 7 then

segmentos <= numero7seg4; -- Saco por Segm el numero2
displays <= "0111"; -- Prendo 2do displays de Derecha a Izquierda.
-- Display Activo =
0L.
cont <= cont + 1; -- Actualizo Contador cnt

elsif cont = 9 then

cont <= 1; -- Reinicio Contador

else

segmentos <= "11111111"; -- Apago todos los segmentos, es

AnodoCom
displays <= "1111"; -- Apago todos los displays. Display Activo=0L
cont <= cont + 1; -- Actualizo Contador cnt
end if;

else

null;
end if;
 end process;

end behaviour;

Componente RelojContador

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Baja loa Frcuencia del Reloj de 50MHz a 1 MHz

entity relojcontador is
port(clk50mhz: IN STD_LOGIC;
clkOUT: INOUT STD_LOGIC);
end relojcontador;

architecture behaviour of relojcontador is

constant max_count: INTEGER := 50000000;
signal count: INTEGER range 0 to max_count;
signal clk_state: STD_LOGIC := '0';

begin
gen_clock: process(clk50mhz, clk_state, count)
begin
if clk50mhz'event and clk50mhz='1' then --if clk50mhz'event and clk50mhz='1'
then
if count < max_count then
count <= count+1;
else
clk_state <= not clk_state;
count <= 0;
end if;
end if;
end process;

persecond: process (clk_state)

begin
clkOUT <= clk_state;
end process;

end behaviour;
Componente Relojbarrido

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Baja loa Frcuencia del Reloj de 50MHz a 1 MHz

entity relojbarrido is
port(clk50mhz: IN STD_LOGIC;
clkOUT: INOUT STD_LOGIC);
end relojbarrido;

architecture behaviour of relojbarrido is

constant max_count: INTEGER := 50000;
signal count: INTEGER range 0 to max_count;
signal clk_state: STD_LOGIC := '0';

begin
gen_clock: process(clk50mhz, clk_state, count)
begin
if clk50mhz'event and clk50mhz='1' then --if clk50mhz'event and clk50mhz='1'
then
if count < max_count then
count <= count+1;
else
clk_state <= not clk_state;
count <= 0;
end if;
end if;
end process;

persecond: process (clk_state)

begin
clkOUT <= clk_state;
end process;

end behaviour;

Componente JK

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clock : in STD_LOGIC;
clear : in std_logic;
q : out STD_LOGIC;
noq : out STD_LOGIC
);
end JK;

architecture proceso of JK is
signal jk : std_logic_vector(1 downto 0) := "00";
signal qsig : std_logic :='0';

begin
jk <= j & k;
process(clear,clock)
begin
if (clear='1')then
qsig <='0';
elsif (clock'event and clock = '1')then
case (jk) is
when "00" => qsig <= qsig;
when "01" => qsig <= '0';
when "10" => qsig <= '1';
when others => qsig <= not qsig;
end case;

end if;
end process;

q <= qsig;
noq<= not qsig;

end proceso;