Staggered Twisted-Bundle Interconnect

for Crosstalk and Delay Reduction

Hao Yu and Lei He

Electrical Engineering Dept.
UCLA

http//:eda.ee.ucla.edu

This work is sponsored by SRC grant (1100.001)

Crosstalk Introduce Delay Variability

Capacitive coupling introduces local ac current-path and

changes delay due to Miller effect
Inductive coupling introduces long-range ac current-path
and further brings delay variation
They could be both controlled by providing local returnpath such as shielding or in a GSG structure such as coplanar wire (CO)
S
G
Gv
i
a

S
G
S

S1 S2
G
Gv
i
a

Silicon substrate

Gv
i
a

S1 S2

i
a

G
S1

Micro-strip T-lines

Gv

S2

Silicon substrate

Coplanar T-lines

Structured Predictable Interconnect

Regular Dense Wire Fabric: Morton DAC99, LSI IEDM02

Power grid
Ground grid
Via (connect shield)
Signal net
Shield net
Cross-under

Power grid acts as ground lines, and cross-under further reduces

coupling

Wide signal line is split into several narrow wires

Increase in area and overall capacitance, and mutual inductance is not

significantly reduced

Increase in delay variation for multiple signal lines signal one shielding
[Sato:ISQED03]
The shielding is not uniform distributed

Interconnect Design Considering Inductance

Control/design the return path to reduce selfinductance

Reducing signal oscillation requires the smallest overall

loop inductance

Return to ground as near as possible, i.e., ground lines need to be close

to signal lines

Reducing delay variation requires each signal line to

have a similar self loop inductance

Return paths need uniformly distributed, i.e., a biased design of ground

lines is not preferred

S1

S2

S3
4

Interconnect Design Considering Inductance

Control and design a wiring pattern to reduce

mutual-inductance

Reducing long-range crosstalk needs to cancel mutual coupled magnetic

flux

Twisted and normal wire (TN)

Twist signal lines with shielding to form polarity-interleaved flux

[Zhong:ICCAD00]
Need additional normal wires to reduce mutual inductance

The mutual coupling between twisted and normal group is reduced

The delay/crosstalk in normal group is still big and varied for each signal net

Technology Aspects of Twisted Interconnect

Twisted wire signaling is wellknown in wired transmission

The challenge of on-chip

implementation comes from
the cost of vias (Al
interconnect)

Telephone line, cable

Tungsten plugs has the via resistance as

large as 100um wire (Al)

Vias

Copper is planned in full sub-0.25 um process flows

and large-scale designs (IBM and Motorola IEDM97 IEDM02)

With cladding and other effects, Cu ~ 2.2 mW-cm vs. 3.5 for Al(Cu) 40%
reduction in resistance
In dual-damascene process via and interconnect are manufactured
simultaneously
Vias in cooper have reduce resistance as well

Our Contribution

Twisted and staggered (TS)

No normal wire group

Reduce both inductive and capacitive coupling uniformly for
each signal net

Measured by a testing chip

TS-interconnect structure reduces delay by 25% and reduces

delay variation by 25X compared to coplanar shielding
TS-interconnect structure reduces delay by 7.5% and reduces
delay variation by 33X compared to TN-interconnect structure

Outline

Motivation to design twisted wire and

staggered twisted-wire

Synthesis of twisted bundle by routing

matrix

Experiment results

Conclusion and future work

A Twisted Pair
m a g n e tic flu x w ith p o la rity +

c a p a c itiv e c o u p lin g
w it h c o u p lin g le n g t h l/2

m a g n e tic flu x w ith p o la rity --

--

tw is te d -p a ir 1

n o rm a l-p a ir 1

T w is ite d -p a ir w ith n o rm a l w ire s

A signal wire is twisted with a shield composed of twisted group

A normal group (with normal signal and shield wires) is used to

achieve a zero mutual inductive coupling [Zhong:ICCAD02]

S h ie ld
A ggressor

0.5l

N l

V ic tim
S h ie ld

A Low-frequency Model
Capacitive coupling

Inductive coupling
Z

Z A src
V A src

IA 1
sM 0 lI A 1

IA 2
sM 0 lI A 2

IA 3
sM 0 lI A 3

Z V src

Z A ld
Z V ld

Z
V

A src

V src

A 1

A 2

A ld

V ld

A ld

A 3

A src

sC

lV

A 1

saC

lV

A 2

sC

lV

A 3

(a ) T h e c o m p le te m o d e l
(a ) T h e c o m p le te m o d e l

Z A src
V A src

IA
V in d u c e d
Z V src

Z A ld
Z V ld

(b ) T h e e q u iv a le n t m o d e l

A src

V
V

A src

I in d u c e d

V src

V ld

( b ) T h e e q u iv a le n t m o d e l

Inductive coupling noise voltage is significantly reduced

Capacitive coupling noise voltage is only reduced by a shielding factor

The capacitive coupling length is still large! 0.5*N*l*(1+)

10

Staggered Twisted Pair

Mutual inductive coupling has the similar reduction as no staggering

s ta g g e re d
tw is te d -p a ir 1
s ta g g e re d
tw is te d -p a ir 2
s ta g g e re d
tw is te d -p a ir 3
s ta g g e re d
tw is te d -p a ir 4
T w is ite d -p a ir w ith s ta g g e rin g

11

Staggered Twisted Pair

Capacitive coupling is reduced

Coupling length is reduced by a factor of staggering stage

s:
0.5*N*l*(1+)/

s
s ta g g e re d
tw is te d -p a ir 1
s ta g g e re d
tw is te d -p a ir 2
s ta g g e re d
tw is te d -p a ir 3
s ta g g e re d
tw is te d -p a ir 4
T w is ite d -p a ir w ith s ta g g e rin g

12

Layout of Twisted Wires

dx

dy

layout for one twist of two signal nets

A symmetrical realistic layout for one twisting between

signal nets using two layers

Achieve uniform delay among each signal net

13

Layout of Twisted Bundle

2d
2d
2d

Power grid
Ground grid
Via (connect shield)
Signal net
Shield net
Cross-under

A twist with signal and shield ratio 3:1

Multiple signal wires share with one shielding to reduce the area cost

Signal/shield ratio (# of signal nets / # of shield nets)

A systematic synthesis of the staggered twisting layout needs to use

routing matrix

14

Outline

Motivation to design twisted wire and

staggered twisted-wire

Synthesis of twisted bundle by routing

matrix

Experiment results

Conclusion and future work

15

Routing Matrix
C o m p le m e n ta r y
N o r m a l C e ll

T w is te d C e ll

C o m p le m e n ta r y
T w is te d C e ll

N o r m a l C e ll

Decompose wire segments into

four cells:
(1) Twisted cell with routing matrix T
(2) Complementary twisted cell with
routing matrix Tb
(3) Normal cell with routing matrix N
(4) Complementary normal cell with
routing matrix Nb

T
N

T
N

T
N

T
N

T
N

T
N

T
N

T
N

T
N

T
N

T
N

T
N

Synthesize each typed group of

wire segments according to
cyclic permutation

16

An Example
Twisted cell with routing matrix T for 3-bit bus with 1 shield

Number each wire with [0,1,2,3]

0 represents for the shield

Decompose each wire into 4 segments such

that it results in a 4x4 array

Entry represents each wire segment with wire

number

Create an initial routing vector T0

A first cyclic permutation of T0 to create a

permutation matrix T

A second cyclic permutation of T with inserted

0 element to create routing matrix T

T0 [3

1]

3 2 1
T ' 1 2 3
2 3 1

0 1 2 3
1 0 3 2

T
2 3 0 1

3
2
1
0

17

Synthesis of Twisted Bundle

The permutation matrix is generally feasible for odd number signal net

We add one dummy wire when there are even number of signal nets

18

An Example
Routing matrix for 12-bit bus with 3:1 signal/shielding ratio

19

Outline

Motivation to design twisted wire and

staggered twisted-wire

Synthesis of twisted bundle by routing

matrix

Experiment results

Conclusion and future work

20

An Accurate Modeling for Twisted Bundle

o u tp u t p o r t 1

in p u t p o r t 1
K

ij

in p u t p o r t 2

( a ) P E E C m o d e l fo r tw is te d w ire s : v ia a n d d o g le g a re m o d e le d a s R L b ra n c h .

o u tp u t p o r t 2

( b ) P E E C m o d e l f o r s ta g g e r e d t w i s t e d w ir e s w it h n o n - l in e a r d r iv e r /r e c e i v e r .

Simple low frequency model can is not accurate at high frequency and can not
handle complicated topology of bundles

The assumption of return at local shield is inaccurate [Zhong:ICCAD00]

coupling capacitance can act as return path between two adjacent signal nets at
high frequency

PEEC model for each segment and model reduction by PRIMA to obtain
macro-model

21

Macro-model of Structured Interconnect

1-stage 18 signal nets with signal/shield ratio 9:1. The input is a 1.8V
exponential voltage source with rising time 50ps

80-pole approximation with 258X speedup (82.9s vs. 20282.41s)

All low-order models have non-negligible error

22

Experiment Settings

We use 180nm (IBM) and 70nm (Berkeley Predictive

Model)
We assume that M6 is used to layout the signals and
shields

The via is chosen as array of the minimum size 0.2um^2

The driver size is about 100X to the minimum inverter

size
RLC extracted FastHenry/FastCap
WCD/WCN determination considering inductance [Chen
and He:TCAD05]

23

Comparison among Structured Interconnect

(1) Coplanar Shielding
shield
signal

(a) 6 bit COPS with signal/shield ratio 3;1

M6
Length: 4000um
Width: 0.3um (min
Spacing:0.4um (min)

24

Comparison among Structured Interconnect

(2) Twisted Bundle
Twisted group

(b) 6-bit TWB with signal/shield ratio 3:1

Normal group

M6
Length: 4000um
Width: 0.3um (min)
Spacing:0.4um (min)
every 1000um for one twist

25

Comparison among Structured Interconnect

(3) Staggered Twisted Bundle

(c) 6-bit STWB with signal/shield ratio 3:1

M6
Length: 4000um
Width: 0.3um (min)
Spacing:0.4um (min)
every box size is 1000um, and inside the box
every 250um for one twist

26

Worst Case Delay/Noise Comparison

COPS
TWB
STWB

worst case delay for each signal

0.6

WCN (normalized to Vdd 1.8)

60
50
WCD (ps)

COPS
TWB
STWB

worst case noise for each signal

40
30
20
10

0.5
0.4
0.3
0.2
0.1
0

0
1

3
4
5
signal net number

3
4
signal net number

STWB has 11ps smaller delay than COPS, and 8ps smaller than TWB

STWB has >15% WCN reduction than TWB, and similar WCN as COPS

STWB has more uniform WCD/WCN at each signal net

27

Impact of Number of Staggering

A small increase of staggering

number can reduce both
WCD/WCN

Staggering becomes saturated

as large staggering number
results in the parasitic of
segmented wire is comparable
to via

A small number of staggering is

preferred as the impact of the
process variation from the via is
also minimized

28

Impact of Signal/Shielding Ratio

Compared to COPS, STWB has

Up to 20% WCD reduction

Better WCN For large signal/shield ratio

Compared to TWB, STWB has

5% and 12% less WCD/WCN value

26% and 28% less WCD/WCN variation

29

Conclusions and Future Work

Design of structural interconnect is needed to

reduce interconnect capacitance and inductance
introduced delay and crosstalk

By uniformly distributing shield with twisting

A staggered twisted-bundle can achieve the reduction of

WCD/WCN
A staggered twisted-bundle can achieve a minimum
WCD/WCN variability among each signal net

A design of test chip is under development based on IBM 0.13um

process

30