Development of Microprocessor

Development of Microprocessor

Combination of digital computer and

semiconductor technology.
By the development of LSI and VLSI
technology, INTEL developed a single
integrated chip that performed all operation
as CPU and was consequently called a P.
 A breakthrough in the development of
microprocessor was achieved in 1972, when
INTEL developed its first P called Intel 4004.
The Intel 4004 was the first chip to contain all
of the components of a CPU on a single chip.
 It is a 4-bit P, i.e. its instruction and data
word length was 4-bit.
It is primarily used in calculators
The Intel 4004 was shortly followed by 8-bit
P 8008 in 1972.
 8080 was 8-bit P, which can operate 20 times
faster than 8008.
8-bit 6800 processor of Motorola in 1974.
After that Intel 8085, 8086, 80186, 80286,
80386, 80486 and Pentium where as Motorola
produced 6802, 68000, etc.
 Chapter 2: Architecture of 8-bit
microprocessor (8085)
Intel 8085 is an 8-bit P.
Components:
- Register
- Accumulator
- Flags
- Program Counter
- Stack pointer
 Instruction decoder
Arithmetic and Logic Unit
Register
The 8085 has six general purpose registers,
one accumulator, one flag register and other
special 8-bit registers.
In addition, it has two 16-bit register: the
program counter and the stack pointer.
 6 general purpose registers: B, C, D, E, H & L.
Accessible to the programmer and can be
used to store/copy data by using instruction.
Can be used individually as 8-bit register or
can be combined as register pair BC, DE, HL to
perform some 16-bit operations.
 Accumulator
8-bit register that is a part of ALU
Used to store 8-bit data and to perform
arithmetic and logical operations.
The result of an operation is stored in the
accumulator.
Also identified as register A.
 Flags
The ALU includes five flip-flops, which are set
or reset after an operation according to data
conditions of the result in the accumulator
and other registers.
They are called Zero(Z), Carry (CY), Sign (S),
Parity (P), and Auxiliary Carry (AC) flags.
 The most commonly used flags are Zero, Carry,
and Sign.
The P uses these flags to test data conditions.
E.g., after an addition of two numbers, if the
sum in the accumulator is larger than eight
bits, the flip-flop uses to indicate a carry called
the Carry flag (CY) is set to one.
 When an arithmetic operation results in zero,
the flip-flop called the Zero(Z) flag is set to
one.
The flags are stored in the 8-bit register so
that the programmer can examine these flags
(data conditions) by accessing the register
through an instruction.
 Program counter
This 16-bit register deals with sequencing the
execution of instructions.
This is a memory pointer
Memory locations have 16-bit addresses, and
that is why this is a 16-bit register.
Used to sequence the execution of the
instructions.
 The function of the program counter is to
point to the memory address from which the
next byte is to be fetched.
When a byte (machine code) is being fetched,
the program counter is incremented by one to
point to the next memory location.
 Stack Pointer
16-bit register used as a memory pointer
It points to a memory location in R/W
memory, called the stack.
The beginning of the stack is defined by
loading 16-bit address in the stack pointer.
Temporary register
8-bit register, which is not accessible to the
programmer.
Used internally by the microprocessor to hold
8-bit data during the execution of some
instruction.
Instruction register
When an instruction is fetched from the
memory, it is loaded in the instruction register.
It passes the instruction to the instruction
decoder & machine cycle encoding circuit.
Instruction Decoder
It decodes the instruction, so that the
microprocessor knows which type of
operation is to be performed before executing
it.
The output of the instruction decoder is fed to
control and timing unit.
The control and timing unit then generates
the necessary control and timing signals.
Arithmetic and Logic Unit
The ALU performs the arithmetic operations
like add, subtract, etc. and logical operations
like AND, OR, XOR, etc.
ALU carries out left & right shifting of the 8-bit
data stored in accumulator.
 When ALU performs arithmetic and logical
operations, one of the data is stored in
accumulator and the result of the operations
is returned to the accumulator itself.
The flags are affected by the arithmetic and
logic operation in ALU.
Pin diagram of 8085 microprocessor
Intel 8085
Properties
Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
- Non-Maskable Interrupt: highest-priority interrupt
capable of interrupting all software and non-vital
hardware devices.
Serial In/ Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K memory
 Intel 8085A is a new generation, complete 8
bit parallel CPU.
Uses a multiplexed data bus.
The address is split between the 8-bit address
bus and the 8 bit data bus.
Pin Description
A6 - A1s (Output 3 State)
Address Bus: The most significant 8 bits of the
memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3 state)
 Multiplexed Address/Data Bus; Lower 8 bits of
the memory address (or I/O address) appear
on the bus during the first clock cycle of a
machine state.
It then becomes the data bus during the
second and third clock cycles. 3 stated during
Hold and Halt modes.
ALE (Output)
Address Latch Enable
- It occurs during the first clock cycle of a
machine state and enables the address to get
latched into the chip latch of peripherals.
- The falling ALE holds time for the address
information.
SO, S1 (Output)
Data Bus Status
Encoded status of the bus cycle:
S1 S0
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status
RD (Output 3state)
READ indicates the selected memory or I/0
device is to be read and that the Data Bus is
available for the data transfer.
WR (Output 3 state)
WRITE indicates the data on the Data Bus is to
be written into the selected memory or I/0
location. Data is set up at the trailing edge of
WR. 3 stated during Hold and Halt modes.
READY (Input)
If Ready is high during a read or write cycle,
the memory or peripheral is ready to send or
receive data.
If Ready is low, the CPU will wait for Ready to
go high before completing the read or write
cycle.
HOLD (Input)
HOLD indicates that another Master is
requesting the use of the Address and Data
Buses.
The CPU, upon receiving the Hold request, will
relinquish the use of buses as soon as the
completion of the current machine cycle.
 Internal processing can continue. The
processor can regain the buses only after the
Hold is removed.
When the Hold is acknowledged, the Address,
Data, RD, WR, and IO/M lines are 3 stated.
HLDA (Output)
HOLD ACKNOWLEDGE indicates that the CPU
has received the Hold request and that it will
relinquish the buses in the next clock cycle.
HLDA goes low after the Hold request is
removed.
The CPU takes the buses one half clock cycle
after HLDA goes low.
INTR (Input)
INTERRUPT REQUEST is used as a general
purpose interrupt.
It is sampled only during the next to the last
clock cycle of the instruction.
If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA will
be issued.
 During this cycle a RESTART or CALL
instruction can be inserted to jump to the
interrupt service routine.
The INTR is enabled and disabled by software.
It is disabled by Reset and immediately after
an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE is used instead of
(and has the same timing as) RD during the
Instruction cycle after an INTR is accepted.
It can be used to activate the 8259 Interrupt
chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS: These three inputs have
the same timing as INTR except they cause an
internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
TRAP (Input)
Trap interrupt is a non-maskable restart
interrupt.
Recognized at the same time as INTR
Unaffected by any mask or Interrupt Enable
Has the highest priority of any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and
resets the Interrupt Enable and HLDA flipflops.
None of the other flags or registers (except
the instruction register) are affected.
The CPU is held in the reset condition as long
as Reset is applied.
RESET OUT (Output)
Indicates CPU is being reset
Can be used as a system RESET
The signal is synchronized to the processor
clock.
X1, X2 (Input)
Crystal or R/C network connections to set the
internal clock generator X1 can also be an
external clock input instead of a crystal
The input frequency is divided by 2 to give the
internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a
crystal or R/ C network is used as an input to
the CPU
The period of CLK is twice the X1, X2 input
period.
IO/M (Output)
IO/M indicates whether the Read/Write is to
memory or l/O Tri-stated during Hold and Halt
modes.
SID (Input)
Serial input data line
The data on this line is loaded into
accumulator bit 7 whenever a memory
instruction is executed.
SOD (output)
Serial output data line
The output SOD is set or reset as specified by
the SIM instruction.
Vcc
+5 volt supply.
Vss
Ground Reference.
 8085 in brief
The 8085 is an 8-bit general purpose
microprocessor that can address 64K Byte of
memory.
40 pins,maximum frequency of 3 MHz
6 groups of pins: Address Bus, Data Bus,
Control and Status Signals, Power supply and
frequency, Externally Initiated Signals, Serial
I/O ports.
 A8 A15 unidirectional.
The other 8 address bits are multiplexed (time
shared) with the 8 data bits.
AD0 AD7 are bi-directional and serve as A0
A7 and D0 D7 at the same time.
 Control and status signals
ALE: Address Latch Enable. This signal is a
pulse that become 1 when the AD0 AD7
RD: Read. Active low.
WR: Write. Active low.
IO/M: memory operation (IO/M=0) or an
I/O operation (IO/M=1).
S1 and S0 : Status signals to specify the
kind of operation
 Frequency Control Signals
3 important pins
X0 and X1 are the inputs from the crystal or
clock generating circuit.
The frequency is internally divided by 2.
So, to run the microprocessor at 3
MHz, a clock running at 6 MHz should
be connected to the X0 and X1 pins.
CLK (OUT): An output clock pin to drive the
clock of the rest of the system.
 Chip Selection
A15- A10 Circuit

8085
CS
A15-A8

ALE
A9 - A0 1K Byte
Latch Memory
AD7-AD0 A7 - A0 Chip

WR RD IO/M D7 - D0
RD WR
 Memory Read and Write.
I/O Read and Write.
Request Acknowledge.
The first step of executing any instruction is
the Opcode fetch cycle.
IO/M=0, s0 and s1 are both 1.
 Memory Read Machine Cycle
The memory read machine cycle is exactly the
same as the opcode fetch except:
It only has 3 T-states
The s0 signal is set to 0 instead.
Memory structure & its requirements
 Interfacing Memory
The microprocessor places a 16-bit address on
the address bus.
Part of the address bus will select the chip and
the other part will go through the address
decoder to select the register.
The signals IO/M and RD combined indicate
that a memory read operation is in progress.
 Address decoding
Chip Selection
A15- A10 Circuit

8085
CS
A15-A8

ALE
A9 - A0 1K Byte
Latch Memory
AD7-AD0 A7 - A0 Chip

WR RD IO/M D7 - D0
RD WR
Control and Status Signals
Interrupt Vectors
 RESET signal
RESET IN: an active low input signal,
Program Counter (PC) will be set to 0 and
thus MPU will reset.
RESET OUT: an output reset signal to
indicate that the p was reset (i.e. RESET
IN=0). It also used to reset external devices.
 Direct Memory Access (DMA)
DMA is an IO technique where external IO
device requests the use of the MPU buses.
Allows external IO devices to gain high speed
access to the memory.
Example of IO devices that use DMA: disk
memory system.
 HOLD and HLDA are used for DMA.
If HOLD=1, 8085 will place it address, data and
control pins at their high-impedance.
A DMA acknowledgement is signaled by
HLDA=1.
MPU Communication and Bus Timing