EE2174: Digital Logic and

Lab
Professor Shiyan Hu
Department of Electrical and Computer
Engineering
Michigan Technological University

Encoder and Decoder

 Overview of Encoder and
Decoder
 MUX Gate
 Rudimentary functions
 Binary Decoders
 Expansion
 Circuit implementation
 Binary Encoders
 Priority Encoders

Apr 22, 202 PJF - 2

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 Multiplexer
 “Selects” binary information from one of
many input lines and directs it to a single
output line.
 Also know as the “selector” circuit,
 Selection is controlled by a particular set of
inputs lines whose # depends on the # of the
data input lines.
 For a 2n-to-1 multiplexer, there are 2n data
input lines and n selection lines whose bit
combination determines which input is
selected.

Combinational
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 Multiplexer (cont.)

Combinational
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 2-to-1-Line Multiplexer
 Since 2 = 21, n = 1
 The single selection variable S has two values:
 S = 0 selects input I0
 S = 1 selects input I1
 The equation:
Y = S’ I0 + SI1
 The circuit:
Enabling
Decoder Circuits

I0
Y
S
I1 Combinational
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Example: 4-to-1 MUX using Cell Library
Based Design

Combinational
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 4–to–1-Line Multiplexer
using Transmission Gates

Combinational
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 MUX as a Universal Gate
 We can construct AND and NOT gates using
2-to-1 MUXs. Thus, 2-to-1 MUX is a universal
gate.

z = 0x + 1x’ = x’ z = x1x0 + 0x0’ = x1x0

Apr 22, 202 Combinational Logic PJF - 8

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Multiple Bit Selection
 Until now, we have examined single-bit
data selected by a MUX. What if we
want to select m-bit data/words?
 Combine MUX blocks in parallel with
common select and enable signals
 Example: Construct a logic circuit that
selects between 2 sets of 4-bit inputs
(see next slide for solution).

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 Example: Quad 2-to-1 MUX
 Uses four 4-to-1
MUXs with common
select (S) and enable
(E).
 Select line chooses
between Ai’s and Bi’s.
The selected four-
wire digital signal is
sent to the Yi’s
 Enable line turns MUX
on and off (E=1 is on).

Apr 22, 202 PJF - 10

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Implementing Boolean functions
with Multiplexers
 Any Boolean function of n variables can
be implemented using a 2n-1-to-1
multiplexer. A MUX is basically a
decoder with outputs ORed together,
hence this isn’t surprising.
 The SELECT signals generate the
minterms of the function.
 The data inputs identify which minterms
are to be combined with an OR.
Apr 22, 202 PJF - 11
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 Example
•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)
•There are n=3 inputs, thus we need a 22-to-1 MUX
•The first n-1 (=2) inputs serve as the selection lines

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 Efficient Method for
implementing Boolean functions
 For an n-variable function (e.g., f(A,B,C,D)):
 Need a 2n-1 line MUX with n-1 select lines.
 Enumerate function as a truth table with consistent ordering
of variables (e.g., A,B,C,D)
 Attach the most significant n-1 variables to the n-1 select
lines (e.g., A,B,C)
 Examine pairs of adjacent rows (only the least significant
variable differs, e.g., D=0 and D=1).
 Determine whether the function output for the (A,B,C,0) and
(A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1).
 Attach 0, D, D’, or 1 to the data input corresponding to
(A,B,C) respectively.

Apr 22, 202 PJF - 13

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 The Other Example
 Consider F(A,B,C) = m(1,3,5,6). We can
implement this function using a 4-to-1
MUX as follows.
 The index is ABC. Apply A and B to the
S1 and S0 selection inputs of the MUX
(A is most sig, S1 is most sig.)
 Enumerate function in a truth table.

Apr 22, 202 PJF - 14

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 MUX Example (cont.)
A B C F
0 0 0 0
When A=B=0, F=C 0 0 1 1
0 1 0 0
When A=0, B=1, F=C 0 1 1 1
1 0 0 0
When A=1, B=0, F=C 1 0 1 1
1 1 0 1
When A=B=1, F=C’ 1 1 1 0

Apr 22, 202 PJF - 15

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MUX implementation of F(A,B,C)
= m(1,3,5,6)
B
A

C
C
F
C
C’
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 A larger Example

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 Rudimentary Functions

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 Selection

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 Enabling
 “gating” ?

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 The Other Code Converter
BCD-to-Seven-Segment Converter
 Seven-segment display:
 7 LEDs (light emitting diodes), each one
controlled by an input a
 1 means “on”, 0 means “off”
f b
 Display digit “3”?
g
 Set a, b, c, d, g to 1
 Set e, f to 0 e c

d
Apr 22, 202 PJF - 21
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BCD-to-Seven-Segment Converter

 Input is a 4-bit BCD code  4 inputs (w,

x, y, z).
 Output is a 7-bit code (a,b,c,d,e,f,g) that
allows for the decimal equivalent to be
displayed. a
 Example: f g b
 Input: 0000BCD
 Output: 1111110 e c
(a=b=c=d=e=f=1, g=0)
d
Apr 22, 202 PJF - 22
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 BCD-to-Seven-Segment (cont.)
Truth Table
Digit wxyz abcdefg Digit wxyz abcdefg
0 0000 1111110 8 1000 1111111
1 0001 0110000 9 1001 111X011
2 0010 1101101 1010 XXXXXXX
3 0011 1111001 1011 XXXXXXX
4 0100 0110011 1100 XXXXXXX
5 0101 1011011 1101 XXXXXXX
6 0110 X011111 1110 XXXXXXX
7 0111 11100X0 1111 XXXXXXX
??
Apr 22, 202 PJF - 23
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 Decoders
 A combinational circuit that converts
binary information from n coded inputs
to a maximum 2n coded outputs
 n-to- 2n decoder
 n-to-m decoder, m ≤ 2n
 Examples: BCD-to-7-segment decoder,
where n=4 and m=10

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 Decoders (cont.)

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 1-2 Decoder

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 2-to-4 Decoder

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 2-to-4 Active Low Decoder

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 3-to-8 Decoder
address

data
Apr 22, 202 PJF - 29
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 3-to-8 Decoder (cont.)
 Three inputs, A0, A1, A2, are decoded into
eight outputs, D0 through D7
 Each output Di represents one of the
minterms of the 3 input variables.
 Di = 1 when the binary number A2A1A0 = i
 Shorthand: Di = mi
 The output variables are mutually exclusive;
exactly one output has the value 1 at any time,
and the other seven are 0.

Apr 22, 202 PJF - 30

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 Decoder Expansion

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 Decoder with enable

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Implementing Boolean functions
using decoders
 Any combinational circuit can be constructed
using decoders and OR gates! Why?
 Here is an example:
Implement a full adder circuit with a decoder
and two OR gates.
 Recall full adder equations, and let X, Y, and Z
be the inputs:
 S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
 C (X,Y,Z) = m(3, 5, 6, 7).
 Since there are 3 inputs and a total of 8
minterms, we need a 3-to-8 decoder.
Apr 22, 202 PJF - 33
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 Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = SUM m(1,2,4,7)
C(X,Y,Z) = SUM m(3,5,6,7)

Apr 22, 202 PJF - 34

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 Encoders
 An encoder is a digital circuit that
performs the inverse operation of a
decoder. An encoder has 2n input lines
and n output lines.
 The output lines generate the binary
equivalent to the input line whose value
is 1.

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 Encoders (cont.)

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 Encoder Example
 Example: 8-to-3 binary encoder (octal-to-binary)

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
Apr 22, 202 PJF - 37
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 Encoder Example (cont.)

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 Encoder Design Issues
 There are two ambiguities associated with
the design of a simple encoder:
1. Only one input can be active at any given time. If
two inputs are active simultaneously, the output
produces an undefined combination (for example,
if D3 and D6 are 1 simultaneously, the output of
the encoder will be 111.
2. An output with all 0's can be generated when all
the inputs are 0's,or when D0 is equal to 1.

Apr 22, 202 PJF - 39

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 Priority Encoders
 Solves the ambiguities mentioned above.
 Multiple asserted inputs are allowed;
one has priority over all others.
 Separate indication of no asserted
inputs.

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Example: 4-to-2 Priority Encoder
Truth Table

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4-to-2 Priority Encoder (cont.)
 The operation of the priority encoder is
such that:
 If two or more inputs are equal to 1 at
the same time, the input in the highest-
numbered position will take precedence.
 A valid output indicator, designated by
V, is set to 1 only when one or more
inputs are equal to 1. V = D3 + D2 + D1 +
D0 by inspection.

Apr 22, 202 PJF - 42

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Example: 4-to-2 Priority Encoder
K-Maps

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Example: 4-to-2 Priority Encoder
Logic Diagram

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 8-to-3 Priority Encoder

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Uses of priority encoders (cont.)

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 Link Between Multiplexer and
Decoder
 Note the regions of the multiplexer
 1-to-2-line Decoder
 2 Enabling circuits
 2-input OR gate
 In general, for an 2n-to-1-line multiplexer:
 n-to-2n-line decoder
 2n AND gates
Enabling
Decoder Circuits

I0
Y
S
I1

Apr 22, 202 PJF - 47

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 Summary of Encoder and
Decoder
 MUX Gate
 Rudimentary functions
 Binary Decoders
 Expansion
 Circuit implementation
 Binary Encoders
 Priority Encoders

Apr 22, 202 PJF - 48

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