Lectures on
Input-Output Organization
UNIT 8
Peripheral Devices
Keyboard
Monitor
Printer
Magnetic Disks etc…
ASCII
INPUT-OUTPUT INTERFACE
Computer Requires special communication links because
1. The manner of operation of Peripheral is different than CPU.
2. The data transfer rate is slower than CPU.
3. Data codes and formats in peripherals differ from the CPU word format.
4. The operating modes are different for each peripheral and one must not
disturb other peripheral while operating on one.
I/O BUS
Bus Contains:
DATA
ADDRESS
CONTROL
Interface contain appropriate circuit modules
& Address decoder for Peripherals
Standard Words I/O Bus
I/O command
Control Command
Status Command
Output Data
Input data
I/O vs Memory Bus
3 ways to communicate
1. 2 separate buses one for Memory & One for I/O
2. Common bus for both but separate control lines for each
3. Common bus with common control lines
Isolated v/s Memory Mapped I/O
Isolated I/O Memory Mapped I/O
I/O write and I/O read lines are enabled for No separated lines
I/O operations & Memory write and read lines
enabled for memory operations
CPU has distinct I/O instructions
No I/O instructions so can use memory
instruction to treat I/Os.
Isolates addresses of memory and doesn’t Same memory space for everything
affect on each interface address.
Example of I/O
Interface Unit
Asynchronous Data Transfer
Method 1: Using Strobe pulse/ Signal: Control
signal
Method 2: Using Handshaking Signals:
Data with control signal to indicate the data
and after receiving Acknowledgement from
Destination in form of control signal
Asynchronous Data Transfer using
Handshaking
Serial Transfer
Can be Synchronous or Asynchronous
In synchronous 2 units share common clock frequency and bits are transmitted
continuously at the rate of clock pulses.
Synchronization signals are transmitted periodically to keep their clock in step
In asynchronous binary information is sent only when there is data otherwise line remains
idle
Asynchronous Serial Transfer
3 fields:
Start bit
Character bits
Stop bits
A transmission can be detected using the following rules:
1. When there is no character keep the line at 1-state.
2. Initiation will be detected via zero level which is start bit.
3. Character bits always follow the start bit
4. After the last bit , a stop bit is detected when the line goes to 1 for at least one bit time.
Asynchronous Serial Transfer
Baud rate UART
The rate at which serial information is Universal Asynchronous Receiver Transmitter
transmitted and is equivalent to data transfer Circuit to provide the interface between
per second.
computers and such interactive terminals.
Example: 10 character per second with 11-bit
format has 110 Baud rate (bps)
Modes of Transfer
3- Data Transfer between CPU and I/O devices
Possible Modes:
may be handled in variety of modes.
1. Programmed I/O Some modes are using CPU as intermediate
path.
2. Interrupt- Initiated I/O
3. Direct Memory Access
(DMA)
Programmed I/O
=> Each data transfer is initiated by an instruction in the program.
=> Once a data transfer is initiated, the CPU is required to monitor
the interface to see when a transfer can again be made.
ÞIn the programming I/O , the CPU stays in loop until the I/O
unit indicates it is ready for transfer.
Interrupt Initiated I/O
Priority ?
Priority Encoder
Daisy Chain Priority
Vector Addresses
Each Device is allocated
With its vector address.
Interrupt Initiated I/O
Starting Sequence Ending Sequence
1. Clear Interrupt enable bit IEN.
1. Clear the lower level mask registers 2. Restore contents of processor registers
2. Clear Interrupt status bit 3. Clear the bit in interrupt register belonging to
the source that has been serviced.
3. Save contents of Processor Registers
4. Set lower-level priority bits in the mask
4. Set Interrupt Enable bit IEN. register.
5. Proceed with service routine. 5. Restore return address into Pc and set IEN.
Direct Memory Access (DMA)
To transfer large block of data at high speed, a
special control unit may be provided to allow
transfer of a block of data directly between an
external device and the main memory, without
continuous intervention by the processor. This
approach is called direct memory access or DMA.
DMA transfers are performed by a control circuit associated with the I/O device and this circuit
is referred as DMA controller. The DMA controller allows direct data transfer between the device
and the main memory without involving the processor.
Questions can be asked
1.Explain asynchronous data transfer using timing diagrams.
2. Differentiate synchronous and asynchronous data transfer with examples.
3. Write a detailed note on Direct Memory Access (DMA).
4. Briefly explain source initiated transfer using handshaking.
5. What is asynchronous data transfer? Differentiate between strobe control method and
handshaking method.
6. Differentiate isolated I/O and memory mapped I/O
7. Differentiate Programmed I/O and Interrupt initiated I/O
THANK you
Read Chapter 11 from
Questions?
“Computer System
Architecture” 3rd Edition By M.
Morris Mano
