Itanium Processor
DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING
TRIDENT ACADEMY OF TECHNOLOGY,BHUBANESWAR
Presented by
Name-Mohammad faizan akhter
Branch-ETC(section)
Semester- 6th
Regd No-1801289179
Contents
INTRODUCTION
ARCHITECTURE
MEMORY ARCH:
INSTRUCTION
FORMAT
INSTRUCTION EXECUTION
PIPELINE STAGES:
FLOATING POINT PERFORMANCE
INTEGER PERFORMANCE
CONCLUSION
REFERENCES
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Introduction
• Itanium is the brand name for 64-bit intel
microprocessor that implement the intel
itanium architecture (formerly called IA-
64).
• Itanium's architecture differs dramatically from
the x86 architectures (and the x86-64
extensions) used in other intel processors.
• The architecture is based on explicit instruction-
level parallelism, in which the compiler makes
the decisions about which instructions to
execute in parallel
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Itanium Processor
• First implementation of IA-64
• Compiler based exploitation of ILP
• Also has many features of
superscalar
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Memory architecture
From 2002 to 2006, Itanium 2 processors shared a
common cache hierarchy. They had 16 kb of Level 1
instruction cache . The L2 cache was unified,
(both instruction and data) and is 256 KB. The Level
3 cache was also unified and varied in size from 1.5
MB to 24 MB. The 256 KB L2 cache contains
sufficient logic to handle SEMAPHONE operations
without disturbing the main (ALU).
Main memory is accessed through a bus to an off-
chip chipset. The Itanium 2 bus was initially called
the McKinley bus, but is now usually referred to as
the Itanium bus. The speed of the bus has increased
steadily with new processor releases. The bus
transfers 2x128 bits per clock cycle, so the 200 MHz
McKinley bus transferred 6.4 GB/sand the 533 MHz
Montecito bus transfers 17.056 GB/s .
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Instruction execution
• Each 128-bit instruction word
contains three instruction
• When the compiler can take
maximum advantage of this, the
processor can execute six instructions
per clock cycle.
• The processor has thirty functional
execution units in eleven groups.
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Pipeline Stages
• It has a 10-stage pipeline..
• The most important stages are given
below..
• Front-end
• Instruction delivery
• Operand delivery
• Execution
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Front-end
• Prefetches up to 32 bytes per
cycle (2 bundles) into a
prefetch buffer (up to hold 8
bundles)
• Branch prediction is done
using a multilevel adaptive
predictor
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Instruction delivery
• Distributes up to 6 instructions to
the 9 functional units
• Implements registers
renaming for both rotation and
register stacking.
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Operand delivery
• Accesses the register
file
• Performs register
bypassing
• Accesses and updates
a register score board
• Checks predicate
dependences.
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Execution
• Executes instructions through ALU and load or
store units
• Detects exceptions.
• Retires instructions and performs write-back
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• Large code size
Conclusion
• Only static instruction-level parallelism
• Cannot manage cache misses/hits flexibly
• Lack of applications
• Good floating point performance
• Poor integer performance
• Overall: not so good as Intel has
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REFERENCE
• http://
www.123seminarsonly.com/CS/Itanium-Processor.
html
• https://en.wikipedia.org/wiki/Itanium
• https://www.skillshare.com/browse/processing
• H. Sharangpani and H. Arora, "Itanium processor
microarchitecture," in IEEE Micro, vol. 20, no. 5,
pp. 24-43, Sept.-Oct. 2000, doi:
10.1109/40.877948.
THANK YOU
Itanium processor
