The ARM Architecture
In this lecture
Introduction
ARM Programmer’s Model
ARM Instruction Set
ARM Ltd
Founded in November 1990
Spun out of Acorn Computers
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the
design-in of the ARM architecture
Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc
Introduction
Many devices
are powered by
ARM processors
E.g.
Samsung galaxy S4 ----- ARM Cortex-A15/Cortex-A7
IPhone 4 -------- ARM Cortex-A8
Ipad mini ------- ARM Cortex-A9
Introduction…cntd
ARM is a Reduced Instruction Set Computer (RISC)
A large uniform register file
A load/store architecture
Simple addressing modes
Uniform and fixed-length instruction fields
Some enhancements of ARM to basic RISC architecture
Conditional execution of all instructions
Load and store multiple instructions
Variable cycle execution for certain instructions
Thumb 16-bit instruction set
Enhanced instructions (e.g. enhanced DSP instructions)
ARM Versions
ARM Core Block Diagram
ARM Registers
General-purpose registers
37 32-bit registers
At any one time only 16 of these registers are visible (r0 – r15)
Some of these registers have special functions
Register r13 is used as stack pointer (sp)
Register r14 is called the link register (lr) and is where the core puts the return
address whenever it calls a subroutine
Register r15 is the program counter (pc) and contains the address of the next
instruction
Program status registers
Current Program Status Register (CPSR)
Saved Program Status Register (SPSR)
ARM Processor Modes
ARM has seven basic operating modes
Each mode has access to its own stack space and a different subset of registers
Some operations can only be carried out in a privileged mode
Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes
Entered when a high priority (fast) interrupt is
FIQ
raised
IRQ Entered when a normal priority interrupt is raised
Privileged
modes
Abort Used to handle memory access violations
Undef Used to handle undefined instructions
Privileged mode using the same registers as User
System
mode
Mode under which most Applications / OS tasks Unprivileged
User
run mode
The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1 ARM has 37 registers, all 32-bits long
r2
r3
A subset of these registers is accessible in
each mode
r4
r5 Note: System mode uses the User mode
register set.
r6
r7 SPSR registers are used to save CPSR
of previous mode
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
Current mode Banked out registers
CPSR Register
Condition flags Interrupt masks
N = Negative result from ALU I Disables IRQ interrupt
Z = Zero result from ALU F Disables FRQ interrupt
C = ALU operation Carried out T = 1 indicates Thumb execution
V = ALU operation oVerflowed Mode bits determine the mode in
Which the processor operates
ARM Exceptions
Exception
Any condition that needs to halt the normal sequential execution of instructions
Five types of exceptions in ARM
Each exception changes the processor mode
When an exception occurs it is handled by an exception handler routine
Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
0x1C FIQ
Change to ARM state
0x18 IRQ
Change to exception mode
0x14 (Reserved)
Disable interrupts (if appropriate)
0x10 Data Abort
Stores the return address in LR_<mode>
0x0C Prefetch Abort
Sets PC to vector address 0x08 Software Interrupt
0x04 Undefined Instruction
To return, exception handler needs to:0x00 Reset
Restore CPSR from SPSR_<mode> Vector Table
Vector table can be at
Restore PC from LR_<mode> 0xFFFF0000 on ARM720T
and on ARM9/10 family
This can only be done in ARM state. devices
ARM Instruction Set
Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode (8-bit instructions)
Program Counter (r15)
When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction
cannot be halfword or byte aligned)
When the processor is executing in Thumb state:
All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction
cannot be byte aligned)
When the processor is executing in Jazelle state:
All instructions are 8 bits wide
Processor performs a word access to read 4 instructions at once
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Instruction Set
Different types of instructions
Data processing instructions
Load-store instructions
Branch instructions
Software interrupt instruction
Program status register instructions
Some unique features of arm ISA
Conditional execution
Barrel shifter
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Data Processing Instructions
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons:CMP CMN TST TEQ
Data movement: MOV MVN
These instructions only work on registers, NOT memory.
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd
Data movement does not specify Rn
Second operand is sent to the ALU via a barrel shifter.
Conditional Execution and Flags
ARM instructions can be made to execute conditionally by postfixing them with the
appropriate condition code field.
This improves code density and performance by reducing the number of forward
branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip
By default, data processing instructions do not affect the condition code flags but the
flags can be optionally set by using “S”. CMP does not need “S”.
loop
…
SUBS r1,r1,#1 decrement r1 and set flags
BNE loop
if Z flag clear then branch
Condition Codes
The possible condition codes are listed below
Note AL is the default and does not need to be specified
Suffix Description Flags tested
EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Minus N=1
PL Positive or Zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 & Z=0
LS Unsigned lower or same C=0 or Z=1
GE Greater or equal N=V
LT Less than N!=V
GT Greater than Z=0 & N=V
LE Less than or equal Z=1 or N=!V
AL Always
Conditional Execution Examples
C source code ARM instructions
unconditional conditional
if (r0 == 0) CMP r0, #0 CMP r0, #0
{ BNE else ADDEQ r1, r1, #1
r1 = r1 + 1; ADD r1, r1, #1 ADDNE r2, r2, #1
} B end ...
else else
{ ADD r2, r2, #1
r2 = r2 + 1; end
} ...
5 instructions 3 instructions
5 words 3 words
5 or 6 cycles 3 cycles
More
Examples
Use a sequence of several conditional instructions
if (a==0) func(1);
CMP r0,#0
MOVEQ r0,#1
BLEQ func
Set the flags, then use various condition codes
if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
Use conditional compare instructions
if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0
The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift
CF Destination 0 Destination CF
Multiplication by a power of 2 Division by a power of 2,
preserving the sign bit
LSR : Logical Shift Right ROR: Rotate Right
...0 Destination CF Destination CF
Division by a power of 2 Bit rotate with wrap around
from LSB to MSB
RRX: Rotate Right Extended
Destination CF
Single bit rotate with wrap around
from CF to MSB
Using a Barrel Shifter:TheRegister,
2nd Operand
optionally with shift operation
Operand Operand Shift value can either be:
1 2 5 bit unsigned integer
Specified in bottom byte of
another register.
Barrel
Shifter Used for multiplication by
constant
(r0 = r1+r1*8 = 9*r1)
e.g.
MOV r0,r1,LSL#2 (r0 = r1*4)
ALU
ADD r0, r1, r1, LSL#3
Result
