Chapter 4

MARIE: An
Introduction to a
Simple Computer
4.5 The Input/Output Subsystem

• A computer communicates with the outside world

through its input/output (I/O) subsystem.
• These devices are not connected directly to the CPU. I/O
devices connect to the CPU through various interfaces.
• This exchange of data is performed in two ways.
• I/O can be memory-mapped-- where the I/O device
behaves like main memory from the CPU’s point of
view.

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Or I/O can be instruction-based, where
the CPU has a specialized I/O
instruction set.
Although this does not use memory space,
it requires specific I/O instructions, which
implies it can be used only by CPUs that
can execute these specific instructions.

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 4.6 Memory Organization

• Computer memory envision as a matrix of bits. Each

row, implemented by a register, has a length typically
equivalent to the word size of the machine. Each
register has a unique address;
• memory addresses usually start at zero and progress
upward..

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• Memory can be byte-addressable, which
means that each individual byte has a unique
address
• word-addressable, where a word typically
consists of two or more bytes. which means
each word (not necessarily each
• byte) has its own address,

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• Memory is constructed of RAM chips,
often referred to in terms of length 
width.
• If the memory word size of the machine
is 16 bits, then a 4M  16 RAM chip
gives us 4 megabytes of 16-bit memory
locations.

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• Main memory is usually larger than one RAM
chip. Consequently, these chips are combined into
a single memory module to give the desired
memory size. For example, suppose you need to
build a 32K x 16 memory and all you
have are 2K x 8 RAM chips.
You could connect 16 rows and 2 columns of
chips together.

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 4.6 Memory Organization

• Physical memory usually consists of more than one

RAM chip.
• Access is more efficient when memory is organized
into banks of chips with the addresses interleaved
across the chips
• With low-order interleaving, the low order bits of the
address specify which memory bank contains the
address of interest.
• Accordingly, in high-order interleaving, the high order
address bits specify the memory bank.
The next slide illustrates these two ideas.
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 4 Memory Organization

• Main memory usually consists of more than one RAM

chip
– Hence if you buy memory to upgrade you buy a
Memory Module
• Access is more efficient when memory is organized into
banks of chips with the addresses interleaved across the
chips
• in high-order interleaving, the high order address bits
specify the memory bank/module

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 4.6 Memory Organization
• Using high-order interleave
– The advantage of high-order interleave is that two different devices, working on
two different areas of memory, can perform their memory accesses
simultaneously
– e.g., one device accesses address 5 and another accesses 31
• low-order interleave
– the low order bits of the address specify which memory bank contains the
address of interest
– Consecutive memory locations are on consecutive chips
– The advantage of lower-order interleave is that several consecutive memory
accesses can be performed simultaneously
– For instance, fetching 4 consecutive instructions at one time

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4.6 Memory Organization

Low-Order Interleaving

High-Order Interleaving
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 4.7 Interrupts

• The normal execution of a program is altered when

an event of higher-priority occurs. The CPU is
alerted to such an event through an interrupt.
• Interrupts can be triggered by I/O requests,
arithmetic errors (such as division by zero), or when
an invalid instruction is encountered.
• Each interrupt is associated with a procedure that
directs the actions of the CPU when an interrupt
occurs.
– Nonmaskable interrupts are high-priority interrupts that
cannot be ignored.

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 4.8 MARIE

• We can now bring together many of the ideas that

we have discussed to this point using a very simple
model computer.
• Our model computer, the Machine Architecture that
is Really Intuitive and Easy, MARIE, was designed
for the singular purpose of illustrating basic computer
system concepts.
• While this system is too simple to do anything useful
in the real world, a deep understanding of its
functions will enable you to comprehend system
architectures that are much more complex.
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 4.8 MARIE

The MARIE architecture has the following

characteristics:
• Binary, two's complement data representation.
• Stored program, fixed word length data and
instructions.
• 4K words of word-addressable main memory.
• 16-bit data words.
• 16-bit instructions, 4 for the opcode and 12 for the
address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.

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 4.8 MARIE

MARIE’s seven registers are:

• Accumulator, AC, a 16-bit register that holds a
conditional operator (e.g., "less than") or one operand
of a two-operand instruction.
• Memory address register, MAR, a 12-bit register that
holds the memory address of an instruction or the
operand of an instruction.
• Memory buffer register, MBR, a 16-bit register that
holds the data after its retrieval from, or before its
placement in memory.

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 4.8 MARIE

MARIE’s seven registers are:

• Program counter, PC, a 12-bit register that holds the
address of the next program instruction to be
executed.
• Instruction register, IR, which holds an instruction
immediately preceding its execution.
• Input register, InREG, an 8-bit register that holds data
read from an input device.
• Output register, OutREG, an 8-bit register, that holds
data that is ready for the output device.

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 4.8 MARIE

This is the MARIE architecture shown graphically.

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 4.8 MARIE

This is the MARIE data

path shown graphically.

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 4.8 MARIE

• A computer’s instruction set architecture (ISA)

specifies the format of its instructions and the
primitive operations that the machine can perform.
• The ISA is an interface between a computer’s
hardware and its software.
• Some ISAs include hundreds of different instructions
for processing data and controlling program
execution.
• The MARIE ISA consists of only thirteen instructions.

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 4.8 MARIE

• This is the format

of a MARIE instruction:

• The fundamental MARIE instructions are:

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 4.8 MARIE

• This is a bit pattern for a LOAD instruction as it would

appear in the IR:

• We see that the opcode is 1 and the address from

which to load the data is 3.

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 4.8 MARIE

• This is a bit pattern for a SKIPCOND instruction as it

would appear in the IR:

• We see that the opcode is 8 and bits 11 and 10 are

10, meaning that the next instruction will be skipped if
the value in the AC is greater than zero.

What is the hexadecimal representation of this instruction?

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 4.8 MARIE

• Each of our instructions actually consists of a

sequence of smaller instructions called
microoperations.
• The exact sequence of microoperations that are
carried out by an instruction can be specified using
register transfer language (RTL).
• In the MARIE RTL, we use the notation M[X] to
indicate the actual data value stored in memory
location X, and  to indicate the transfer of bytes to a
register or memory location.

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 4.8 MARIE

• The RTL for the LOAD instruction is:

MAR  X
MBR  M[MAR]
AC  MBR

• Similarly, the RTL for the ADD instruction is:

MAR  X
MBR  M[MAR]
AC  AC + MBR

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 4.8 MARIE

• Recall that SKIPCOND skips the next instruction

according to the value of the AC.
• The RTL for the this instruction is the most complex
in our instruction set:
If IR[11 - 10] = 00 then
If AC < 0 then PC  PC + 1
else If IR[11 - 10] = 01 then
If AC = 0 then PC  PC + 1
else If IR[11 - 10] = 11 then
If AC > 0 then PC  PC + 1

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End of Chapter 4

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