INPUT/OUTPUT

ORGANIZATION

Sindhu K, Dept. of ISE, BMSCE 1

Direct Memory Access

Sindhu K, Dept. of ISE, BMSCE 2

 Direct Memory Access
Direct Memory Access (DMA) transfers the block of
data between the memory and peripheral devices of
the system, without the participation of
the processor.
It is used to transfer large blocks of data at high
speed.
 The unit that controls the activity of accessing
memory directly is called a DMA controller.

Sindhu K, Dept. of ISE, BMSCE 3

Direct Memory Access

Sindhu K, Dept. of ISE, BMSCE 4

Direct Memory Access
Direct Memory Access (DMA):
A special control unit may be provided to transfer a block of data
directly between an I/O device and the main memory, without
continuous intervention by the processor.
Control unit which performs these transfers is a part of the
I/O device’s interface circuit. This control unit is called as a
DMA controller.
DMA controller performs functions that would be normally
carried out by the processor:
For each word, it provides the memory address and all the control
signals.
To transfer a block of data, it increments the memory addresses
and keeps track of the number of transfers.

Sindhu K, Dept. of ISE, BMSCE 5

Direct Memory Access (contd..)
DMA controller can transfer a block of data from an external
device to the processor, without any intervention from the
processor.
However, the operation of the DMA controller must be under the
control of a program executed by the processor. That is, the processor
must initiate the DMA transfer.
To initiate the DMA transfer, the processor informs the DMA
controller of:
Starting address,
Number of words in the block.
Direction of transfer (I/O device to the memory, or memory to the I/O
device).
Once the DMA controller completes the DMA transfer, it
informs the processor by raising an interrupt signal.

Sindhu K, Dept. of ISE, BMSCE 6

Direct Memory Access (contd..)

Registers in a DMA interface

Sindhu K, Dept. of ISE, BMSCE 7
Direct Memory Access
Main
Processor
memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface

Fig. Use of DMA Controller in Computer System

•DMA controller connects a high-speed network to the computer bus.

•Disk controller, which controls two disks also has DMA capability. It provides two
DMA channels.
•It can perform two independent DMA operations, as if each disk has its own DMA
controller. The registers to store the memory address, word count and status and
control information are duplicated.
Sindhu K, Dept. of ISE, BMSCE 8
Direct Memory Access (contd..)
To start a DMA transfer of a block of data from the main
memory to one of the disks, an OS routine writes the address
and word count information into the registers of the disk
controller.
The DMA controller proceeds independently to implement
the specified operation.
When the transfer is completed, this fact is recorded in the
status and control register of the DMA channel by setting the
Done bit.
The status register may also be used to record other
information, such as whether the transfer took place correctly
or errors occurred.

Sindhu K, Dept. of ISE, BMSCE 9

Direct Memory Access (contd..)
Processor and DMA controllers have to use the bus in an
interleaved manner to access the memory.
DMA devices are given higher priority than the processor to access the
bus.
Among different DMA devices, high priority is given to high-speed
peripherals such as a disk or a graphics display device.
Processor originates most memory access cycles on the bus.
DMA controller can be said to “steal” memory access
cycles from the bus. This interleaving technique is called as
“cycle stealing”.
An alternate approach is to provide a DMA controller an
exclusive capability to initiate transfers on the bus, and
hence exclusive access to the main memory. This is known
as the “block or burst mode”.

Sindhu K, Dept. of ISE, BMSCE 10

Direct Memory Access (contd..)
DMA transfer can take place in two modes:
DMA Cycle Stealing
•The DMA controller request for a few cycles the bus i.e.
transferring one or two words preferably when the CPU is not
using memory.
• DMA Controller is said to steal cycles from the CPU.

Sindhu K, Dept. of ISE, BMSCE 11

Direct Memory Access (contd..)
DMA transfer can take place in two modes:
DMA Block Transfer
•The DMA controller transfers the whole block of data without
interruption.
•CPU will be idle during this period as it cannot fetch any
instruction from memory.

Sindhu K, Dept. of ISE, BMSCE 12

Direct Memory Access (contd..)

Sindhu K, Dept. of ISE, BMSCE 13

Direct Memory Access (contd..)
Processor and DMA controllers both need to initiate data
transfers on the bus and access main memory.
A conflict may arise if both processor and DMA controller
or two DMA controllers try to use the bus at the same time
to access memory.
An arbitration procedure is implemented to coordinate the
activities of all devices requesting memory transfers.

Sindhu K, Dept. of ISE, BMSCE 14

Bus arbitration
 The device that is allowed to initiate transfers on the bus at any given
time is called the bus master.
 Bus Arbitration is the process by which the next device to become the
bus master is selected and bus mastership is transferred to it.
 When the current bus master relinquishes its status as the bus master,
another device can acquire this status.
 Two approaches to Bus Arbitration:
 Centralized arbitration:
 A single bus arbiter performs the arbitration.
 Distributed arbitration:
 All devices participate in the selection of the next bus master.

Sindhu K, Dept. of ISE, BMSCE 15

Centralized BusArbitration
• Bus arbiter may be the processor or a separate unit connected to the
bus.
• In figure the Processor contains the bus arbitration circuit.
• Normally, the processor is the bus master, unless it grants bus
membership to one of the DMA controllers.
• DMA controller requests the control of the bus by asserting the Bus
Request (BR) line.
• In response, the processor activates the Bus-Grant1 (BG1) line,
indicating that the controller may use the bus when it is free.
• BG1 signal is connected to all DMA controllers in a daisy chain
fashion.
• BBSY signal is 0, it indicates that the bus is busy. When BBSY
becomes 1, the DMA controller which asserted BR can acquire
control of the bus.

Sindhu K, Dept. of ISE, BMSCE 16

Centralized Bus Arbitration

B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2

Sindhu K, Dept. of ISE, BMSCE 17

Centralized arbitration (contd..)
DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal

BG1 BG1 signal propagates

to DMA#2.
BG2

BBSY

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.

Sequence of events during transfer of bus mastership for the devices

Sindhu K, Dept. of ISE, BMSCE 18

Distributed arbitration
All devices waiting to use the bus share the responsibility of
carrying out the arbitration process.
Each device is assigned a 4-bit ID number.
All the devices are connected using 5 lines, 4 arbitration
lines to transmit the ID, and one line for the Start-
Arbitration signal.
To request the bus a device:
Asserts the Start-Arbitration signal.
Places its 4-bit ID number on the arbitration lines.
The pattern that appears on the arbitration lines is the
logical-OR of all the 4-bit device IDs placed on the
arbitration lines.

Sindhu K, Dept. of ISE, BMSCE 19

Distributed arbitration

Sindhu K, Dept. of ISE, BMSCE 20

Distributed Arbitration

•Arbitration process:
• Each device compares the pattern that appears
on the arbitration lines to its own ID, starting
with MSB.
• If it detects a difference, it transmits 0’s on the
arbitration lines for that and all lower bit
positions.
• The pattern that appears on the arbitration lines
is the logical-OR of all the 4-bit device IDs placed
on the arbitration lines.
Sindhu K, Dept. of ISE, BMSCE 21
Distributed arbitration (contd..)
•Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration lines.
•Device B has the ID 6 and wants to request the bus:
- Transmits the pattern 0110 on the arbitration lines.
•Pattern that appears on the arbitration lines is the logical OR of the patterns:
- Pattern 0111 appears on the arbitration lines.

Arbitration process:
•Each device compares the pattern that appears on the arbitration lines to its own
ID, starting with MSB.
•If it detects a difference, it transmits 0s on the arbitration lines for that and all
lower
bit positions.
•Device A compares its ID 5 with a pattern 0101 to pattern 0111.
•It detects a difference at bit position 1, as a result, it transmits a pattern 0100 on
the
arbitration lines.
•The pattern that appears on the arbitration lines is the logical-OR of 0100 and 0110,
which is 0110.
•This pattern is the same as the device IDof ISE,
Sindhu K, Dept. ofBMSCE
B, and hence B has won the arbitration.
22
Distributed arbitration (contd..)

A – 0101
B – 0110
Logical OR so pattern on the bus will be 0111.

A compares its own id with pattern starting from MSB

0101
0111

0100 – finds mismatch at bit 1 hence changes bit 1 and bit 0 value to 0.

0110 + 0111 = 0110 – hence device b is selected.

Sindhu K, Dept. of ISE, BMSCE 23