Lint
Kartik
Introduction
• Lint in Verilog is a process of static code
analysis to check the correctness and quality
of any RTL code.
• The lint code-checking tools have many
guidelines and rules based on good coding
practices.
• The primary purpose of linting in V LSI
design is to detect issues that can lead to
functional errors, timing violations, and
design flaws
Common Rules
1. Non-synthesizable constructs
2. Unintentional latches
3. Unused declaration
4. Combinational loop
5. Multi driven signals
6. Bit width mismatch
7. Bit overflow
8. Read write race
Non-synthesizable constructs
• Non-synthesizable constructs refer to Example:
code elements or constructs that
cannot be directly translated into
hardware during the synthesis module non_syn_ex(a,b,c);
process.
input a,b;
output c;
• System functions like
$display,$monitor,$read,$write ,$strobe real r = 0.025;
are used for displaying messages or
values during simulation but they do not assign c =r+a+b; endmodule
have hardware representations.
Unintentional latches
Example
• Unintentional latches, also Known as
inferred latches, are undesirable constructs
that can occur in a hardware design when
the synthesis tool cannot determine the
value of a register under certain conditions.
• In this code, you've covered the cases for
2'b00, 2'b01, and 2'b10. However, you
have not provided assignments for all
possible combinations of the in signal
(e.g., 2'b11). If in takes a value not
covered by your case statement, there is no
assignment, and the simulator may infer
latches to retain the previous value.
Combinational loop
Example
• A combinational loop occurs when the
output of a combinational logic gate is fed
back into the same gate or another gate
earlier in the combinational logic path,
creating a loop with no sequential
elements (flip-flops or latches) involved.
• This can lead to race conditions and timing
issues.
Unconnected ports
• This rule issues violation when an Example
instantiation leaves some of the
input/inout ports
dangling/floating.
• Unconnected ports can lead to
undefined behavior in the hardware.
When a port is left unconnected,
its value may be undefined,
and the hardware may exhibit
unpredictable behavior during
simulation and on the actual
device.
• . The synthesis tool may not be able to
determine the functionality of
unconnected ports, impacting the
quality of the resulting hardware.
Multi driven signals
Example
• A multi-driven port in Verilog occurs
when a signal or port is being
driven by multiple drivers
simultaneously.
• This situation can lead to
contention, causing unpredictable
behavior in the circuit.
• This is not synthesizable.
• Multi-driver scenarios can increase
the likelihood of metastability.
• It can lead to signal glitches
Incorrect Sensitivity List
Example
• Missing signals in the sensitivity list
can lead to mis-match between pre
and post synthesis simulations
If the sensitivity list is incomplete and
doesn't include all the signals that are
used inside the block, the simulation
tool might not trigger the block
execution when it should. This can
lead to mismatches between
simulation results and the expected
behavior.
Read-Write Race
• it occurs when same register is read in Example
one block and writes in another.
• Here you are seeing that in one
always block value is assign to a while
simultaneously its value is assign to
b means a is writing and read parallel.
This type of race condition can easily
solved by using nonblocking a
Bit overflow
Example
• Bit overflow in Verilog occurs when
the result of an arithmetic
operation exceeds the bit
width of the destination signal
or variable.
• To prevent bit overflow, it is essential
to ensure that the bit width of the
operands and the destination
variable is wide enough to
accommodate the maximum
possible value resulting from the
operation.
List of some Lint Tools used in the V L S I
industry are given below
• S P YG L A S S from Synopsys
• G A S P E R G O L D from Cadence
• A L I N T P R O from Aldec
• Mentor Graphics (inbuilt with H D L Designer)
Thank you
