Course Title: Digital Integrated
circuit design
Lecture 7:
RC Delay Estimation
Instructor :Dr. Aziza I. Hussein
Spring 2011
Reference:
Weste and Harris, CMOS VLSI Design: A Circuits
and Systems Perspective, AW, 4th edition
Delay Definitions
tpdr:
tpdf:
tpd:
tr:
tf: fall time
Slide 2
Delay Definitions
tpdr: rising propagation delay
From input to rising output crossing V DD/2
tpdf: falling propagation delay
From input to falling output crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD
Slide 3
Delay Definitions
tcdr: rising contamination delay
From input to rising output crossing
VDD/2
tcdf: falling contamination delay
From input to falling output crossing
VDD/2
tcd: average contamination delay
tpd = (tcdr + tcdf)/2
Slide 4
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write
2.0
1.5
1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5
0.0
0.0 200p 400p 600p 800p 1n
Slide 5 t(s)
Delay Estimation
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask “What if?”
The step response usually looks like a 1 st order RC
response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that t = RC
pd
Characterize transistors by finding their effective R
Depends on average current as gate switches
Slide 6
RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
Slide 7
RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesn’t matter as long as you are consistent
Slide 8
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2 Y 2
A
1 1
Slide 9
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C
2C
2C
2 Y 2
A Y
1 1
C
R C
Slide 10
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
Slide 11
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
C
d = 6RC
Slide 12
Example: 3-input NAND
Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
Slide 13
Example: 3-input NAND
Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
Slide 14
Example: 3-input NAND
Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
2 2 2
3
3
3
Slide 15
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
Slide 16
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
3C
3
3C
3C
3
3C
3C
3
3C
3C
Slide 17
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3 9C
5C
3 3C
5C
3 3C
5C
Slide 18
Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
t pd
nodes i
Ri to sourceCi
R1C1 R1 R2 C2 ... R1 R2 ... RN C N
R1 R2 R3 RN
C1 C2 C3 CN
Slide 19
Example: 2-input NAND
Estimate worst-case rising and falling delay of 2-input
NAND driving h identical gates.
2 2 Y
A 2
B 2x h copies
Slide 20
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
Slide 21
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
R
Y
(6+4h)C
t pdr
Slide 22
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
R
Y t pdr 6 4h RC
(6+4h)C
Slide 23
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC
h copies
B 2x 2C
Slide 24
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
R/2
R/2
x
2C
Y
(6+4h)C t pdf
Slide 25
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
x R/2 t pdf 2C R2 6 4h C R2 R2
Y
7 4h RC
R/2 2C (6+4h)C
Slide 26
Delay Components
Delay has two parts
Parasitic delay
6 or 7 RC
Independent of load
Effort delay
4h RC
Proportional to load capacitance
Slide 27
Contamination Delay
Best-case (contamination) delay can be substantially
less than propagation delay.
Ex: If both inputs fall simultaneously
2 2 Y
A 2 6C 4hC
B 2x 2C
R R
Y tcdr 3 2h RC
(6+4h)C
Slide 28
Diffusion Capacitance
we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C
3C 3C 3C 3 3C
Slide 29
Layout Comparison
Which layout is better?
VDD VDD
A B A B
Y Y
GND GND
Slide 30
