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FET DC Biasing

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5 views19 pages

FET DC Biasing

Uploaded by

owassim236
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FET Biasing

Introduction 7.1
• the biasing levels for a silicon transistor configuration can
be obtained using the characteristic equations VBE= 0.7 V, IC= β IB, and IC ≅ IE. The
linkage between input and output variables is provided by β

• For the field-effect transistor, the relationship between input and output quantities
is nonlinear due to the squared term in Shockley’s equation.

• The nonlinear relationship between ID and VGS can complicate the mathematical
approach to the dc analysis of FET configurations. A graphical approach may
limit solutions to tenths-place accuracy, but it is a quicker method for most FET
amplifiers

• The general relationships that can be applied to the dc analysis of all FET amplifiers
are IG ≅ 0 A , ID= IS and “Shockley’s equation”
Fixed-Bias Configuration 7.2
Example 7.1
Self-Bias Configuration 7.3
Graphical Approach
Example 7.2
Example 7.3
Voltage Divider Biasing 7.4
Example 7.5
Common-Gate Configuration 7.5
Special case VGS =0 volt 7.6
Q

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