Unit-6
Pin Diagram of 8086
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INTEL 8086 - Pin Diagram
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INTEL 8086 - Pin Details
Power Supply
5V 10%
Ground
Reset
Terminate the
current
activity &
starts
execution
Clock
Timing signal
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INTEL 8086 - Pin Details
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.
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INTEL 8086 - Pin Details
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
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INTEL 8086 - Pin Details
Direct
Memory
Access
Hold
Indicates
the other
master
requesting
for bus
access
Hold
acknowledge
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INTEL 8086 - Pin Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3
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INTEL 8086 - Pin Details
Bus High Enable/S7
Enables most
significant data bits
D15 – D8 during read
or write operation.
S7: Always 1.
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INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins
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Minimum Mode- Pin Details
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Maximum Mode - Pin Details
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory Type of operation
110: write memory being carried out by
111: none -passive the processor.
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Maximum Mode - Pin Details
Lock Output
Used to lock the
peripherals from gaining
DMA
the system bus, when it is
Request/Grant
0.
Lock Output
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Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Indicates the status
of code-prefetch
queue
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• TEST’: If this pin is 0,execution will continue,
else, processor is in idle state. it is a active low
signal.
• READY:it is a active high signal.it indicates
ready for data transfer,when this pin is high.
Minimum Mode 8086 System
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‘Read’ Cycle timing Diagram for Minimum
Mode
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‘Write’ Cycle timing Diagram for Minimum
Mode
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Maximum Mode 8086 System
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Maximum Mode 8086 System
• Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.The Memory, Address Bus,
Data Buses are shared resources between the two processors.
• The control signals for Maximum mode of operation are
generated by the Bus Controller chip 8788. The three status
outputs S0’, S1’, S2’ from the processor are input to 8788.
• The outputs of the bus controller are the Control Signals,
namely DEN, DT/R’, IORC’, IOWTC’, MWTC’, MRDC’, ALE etc.
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Memory Read timing in
Maximum Mode
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Memory Write timing in
Maximum Mode
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Memory Interfacing
Memory Interfacing
Memory Interfacing
Memory Interfacing
Architecture of Programmable I/O Port
8255
PA7 – PA0
Group A Group A
Control Port A
D0-
D7
Data Bus PC7 – PC4
Buffer Group A
Port C
upper
PC3 – PC0
RD Group B
Port C
AO
Lower
Read/
WR Write
PB7 – PB0
Control Group B
A1 Logic Group B
Control
Port B
CS
8255 Programmable I/O Port
• The 8255 is a Programmable peripheral interface
device which is used to control the communication
between microprocessor and i/o devices through
programming using i/o ports.
• 8255 contains 3 ports named as port A, port B and
port C.
• A port is used to communicate between external i/o
device and microprocessor.
• Each port can be used as a input /output port.this can
be achieved by programming the bits of a register is
called control word register.The three ports are
combined into 2 groups.
PIN DIAGRAM OF 8255
Pin Description
PA(0-7): Port A is an I/O port. Its an 8-bit data output
latch/buffer and an 8-bit data input latch.
RD’: Read Control is an Active low input pin. RD is
LOW when CPU reads data.
CS’: Chip Select is an Active low input pin. A
LOW on this pin selects 8255.
GND: This provides the ground for the IC
A0,A1: These pins along with RD’,WR’, CS’ pins
control the operation of 8255. User needs to use these
5 pins to program 8255. following table
indicates the operation of 8255 by using pins A0,A1,
RD’,WR’, CS’.
Pin Description (Accessing 8255 using A0,
A1 ,RD ,WR ,CS pins)
Pin Description
PC(0-7): Port C is an 8-bit I/O port. Its lower 4-bits can be
programmed to work in conjunction with PortB
and the upper 4-bits can be programmed to work in
conjunction with Port A separately.
PB(0-7): Port B is an 8-bit I/O port used for 8-bit output
data latch/buffer or input data buffer
Vcc: +5V power supply.
D7-D0: Data bus, bidirectional, tristate lines connected to system
data lines
RESET: input pin which resets the control word register.
WR’: Write Enable is an active low input pin.it indicates
the write operation.
8255 Ports
Port A
Group A = port A + MSB of port C
Group B = port B + LSB of port C
MSB of Port c LSB ofport c
Port B
Modes of Operation in 8255
• There are two basic modes of operation of 8255.
1.I/O mode
2.Bit set-reset mode: Bit set/reset mode is used
to set resets the port-c bits.
In the I/O mode, 8255 ports works as
programmable I/O ports, while in BSR mode only
port-c(pc0-pc7) cab be used to set or reset its
individual port bits.
Under the I/O mode of operation, further there
are three modes. they are mode0,mode1,mode2.
Modes of Operation in 8255
• 8255 supports three different Modes mode 0, mode 1 and
mode 2.
• Mode 0 (simple I/O)
– This is a simple i/o mode and it provides i/o capability for
all the three ports.
– Any port can be used as input or output port.
– Two 8 bit ports (A&B) and two 4 bit ports (C Upper &
lower) are available.port-c can be used as either single 8-
bitport or two independent 4-bits.
– O/P Ports are latched and I/P ports are not latched
– All the modes can be selected by programming control
word.
Modes of Operation in 8255 Contd..
• Mode 1
– This mode is called strobed i/o mode. Only two ports port-a
&b cab be operated in this mode.
– The hand shaking signals controls i/o action of the
specified port. Port C is used for this purpose
– The Port C lines PC0 – PC2 provides hand shaking signals
for port B .
– The Port C lines PC3 – PC75provides hand shaking signals
for port A .
– Each group contains one 8 bit data I/O port and one 4 bit
control / data port
– 8 bit data port can be used as Input or output port
– Both Input and Output are latched
– PC0-PC2 generates control signals for port B, PC3-PC5
generates control signals for Port A and PC6, PC7 are used
as a simple i/O operation.
Mode 1 control word
When Group A is input
PA7 – PA0
PC4 STBA
INTA PC5 IBFA
PC3 INTRA
RD PC6 - PC7 I/O
Mode 1 control word
When Group B is input
PB7 – PB0
PC2 STBA
INTB PC1 IBFB
PC0 INTRA
RD PC6 - PC7 I/O
Mode 1 control word
When Group A is output
PA7 – PA0
PC7 OBFA
INTA PC6 ACKA
PC3 INTRA
WR PC4 – PC5 I/O
Mode 1 control word
When Group B is output
PB7 – PB0
PC1 OBFB
INTB PC2 ACKB
PC0 INTRB
Modes of Operation in 8255 Contd..
• Mode2
– This is a Strobed bidirectional mode.
– Tha is data will be transmitted & received on an 8 bit data
bus.
– Handshaking signals are provided to maintain proper data
flow and synchronization between data transmitter and
receiver
– In this mode 8-bit bidirectional port A and 5 bits of port C
(PC3 – PC7) are available.
– Three I/O lines are available at port C (PC2-PC0)
– Input and Outputs are both latched
– 5 bit control port C (PC3-PC7) is used for generating /
accepting handshaking signals for 8 bit data transfer on
port A.
Mode 2
PC3 INTR
PA0 – PA7
PC7 OBF
INTE1 PC6
ACK
INTE2 PC4 STB
PC5
IBF
WR
RD PC2 – PC0 I/O
CONTROL WORD for I/O mode
Group B
Port CLSB
0 – output
1 – input
Port B
0 – output
1 – input
Mode of
operation
0 - Mode 0
1 - Mode 1
CONTROL WORD for I/O mode
Group A
Port CUSB
0 – output
1 – input
Port A
0 – output
1 – input
Mode of
operation
00 – Mode 0
01 – Mode 1
10 – Mode 2
11 - Nop
CONTROL WORD for I/O mode
1 – i/0 mode
0 – BSR mode
Checking of the port status
Ex : Write a program to initialize port A and port C
as output to send the data to external devices
and port B as input to receive the data from
input device.
Ans :
1. Define Control word
1 0 0 0 0 0 1 0 = 82 H
CONTROL WORD FORMAT FOR
BSR MODE
X X X Port C
1 – Set
0 0 0 PC0
0 - Reset
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
0 – BSR mode
1 – I/O mode
Interfacing with a Stepper Motor
• A simple scheme for rotating the shaft of a stepper motor is
called a wave scheme
• In this scheme the windings Wa, Wb, Wc, Wd are applied
with required voltage pulses, in a cyclic fashion
• By reversing the sequence of excitation, the direction of the
rotation of the shaft of the stepper motor can be reversed as
shown in the figure
• Working:
– 8255 is interfaced with 8086 in I/O mapped I/O. port C
(PC0, PC1, PC2, PC3) is used to give pulse sequence to
stepper motor. The 8255 provides very less current which
will not be able to drive stepper motor coils so each of the
winding of a stepper motor needs to be interfaced using
high speed switching Darlington transistors with max 1A,
80V rating with heat sink, with the output port of 8255.
Output the sequence in correct order to have the desired
direction to rotate the motor.
Excitation sequences of a stepper motor using wave
switching scheme
Example: To Rotate the stepper motor 180 degrees right and left immediately
and settle down at initial position.
CODE SEGMENT
ASSUME CS:CODE
START: MOV AL,80H
OUT CWR,AL
MOV AL,88H
MOV CX,100
AGAIN1:OUT PORTA,AL
CALL DELAY
ROR AL,1
DEC CX
JNZ AGAIN1
MOV CX,100
AGAIN2:OUT PORTA,AL
CALL DELAY
ROL AL,1
DEC CX
JNZ AGAIN2
INT 3
DELAY: NOP
NOP
MOV BX,0FFFFH
L1: DEC BX
JNZ L1
RET
CODE ENDS
END START
Interrupt Structure of 8086:
• An Interrupt Structure of 8086 can come from
any one the three sources :
• External signal
• Special Instruction in the program
• Condition produced by instruction
• External Signal (Hardware Interrupt)
Interrupt structure of 8086
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Cont…..
• It decrements stack pointer by 2 and pushes the flag register on the stack.
• It disables the INTR interrupt input by clearing the interrupt flag in the flag
• It resets the trap flag in the flag register.
• It decrements stack pointer by 2 and pushes the current code segment
register contents on the stack.
• It decrements stack pointer by 2 and pushes the current instruction
pointer contents on the stack.
• It does an indirect far jump at the start of the procedure by loading the CS
and IP values for the start of the interrupt service routine (ISR).
• An IRET instruction at the end of the interrupt service procedure returns
execution to the main program.
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Interrupt Vector Table 8086
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