UNIT 2

PROGRAMMING OF 8085 PROCESSOR

•Instruction format
•Addressing modes
•Assembly language format
 Instructions
• The program consists of set of instructions stored in the
memory.
• Each instruction specifies an instruction, data and address
• 8085 instruction has two fields. They are
• Operation field/Opcode/ Mnemonics and Operand field
Opcode Operand
It is the part of the instruction that It is called as data or address( 8bit or 16
specify the operation to be performed bit data or address) on which the
E.g.MVI, IN, LDA operation is to be performed.
It is also called as Operation field/ It is called as data
Mnemonics
 Instruction Format
An instruction is a command to the
microprocessor to perform a given task on a
specified data.
Each instruction has two parts: one is
task to be performed, called the operation
code (opcode), and the second is the data to
be operated on, called the operand.
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
One-Byte Instructions
A 1-byte instruction includes the
opcode and operand in the same byte.
Operand(s) are internal register and are
coded into the instruction.
 Two-Byte Instructions
In a two-byte instruction, the first byte
specifies the operation code and the
second byte specifies the operand. Source
operand is a data byte immediately
following the opcode. For example:
 Three-Byte Instructions
In a three-byte instruction, the first byte specifies
the opcode, and the following two bytes specify the 16-
bit address. Here the second byte is the low-order
address and the third byte is the high order address.
opcode + data byte 1+ data byte 2
 8085 Addressing Modes

• Immediate addressing.
• Register addressing.
• Direct addressing.
• Register Indirect addressing.
• Implied Addressing
• Immediate Addressing
In immediate addressing mode, the data
is specified in the instruction itself.
The data will be apart of the program
instruction.
All instructions that have ‘I’ in their
mnemonics are of Immediate addressing type.
• Eg.MVI B, 3EH- Move the data 3EH given in
the instruction to B register.
• Direct Addressing
In direct addressing mode, the address of the
data is specified in the instruction.
The data will be in memory.
In this addressing mode, the program
instructions and data can be stored in different
memory blocks. This type of addressing can be
identified by 16- bit address present in the
instruction.
• Eg.LDA 1050H- Load the data available in memory
location 1050H in accumulator.
• Register Addressing
In register addressing mode, the
instruction specifies the name of the register in
which the data is available.
This type of addressing can be identified
by register names (such as ‘A’, ‘B’....) in the
instruction.
• Eg. MOV A, B -Move the content of B register
to A register.
• MOV destination, source
• Register Indirect Addressing
In register indirect addressing mode, the
instruction specifies the name of the register in
which the address of the data is available.
Here the data will be in memory and the
address will be in the register pair. This type of
addressing can be identified by letter ‘M’
present in the instruction.
• Eg. MOV A, M - The memory data addressed
by HL pair is moved to A register.
• Implied Addressing
In implied addressing mode, the
instruction itself specifies the type of operation
and location of data to be operated.
This type of instruction does not have
any address, register name, immediate data
specified along with it.
Eg. CMA - Complement the content of
accumulator
INSTRUCTION SET OF 8085
BINARY TO DECIMAL NUMBER FORMAT
8 4 2 1 DECIMAL 8 4 2 1 DECIMAL

0 0 0 0 =0 1 0 0 0 =8

0 0 0 1 =1 1 0 0 1 =9

0 0 1 0 =2 1 0 1 0 = 10 = A

0 0 1 1 =3 1 0 1 1 = 11 = B

0 1 0 0 =4 1 1 0 0 = 12 = C

0 1 0 1 =5 1 1 0 1 = 13 = D

0 1 1 0 =6 1 1 1 0 = 14 = E

0 1 1 1 =7 1 1 1 1 = 15 = F
 What is Instruction ?????
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.

• 8085 has 246 instructions.

• Each instruction is represented by an 8-bit

binary value.
Classification Of Instruction Set
• There are 5 Types,

• (1) Data Transfer Instruction,

• (2) Arithmetic Instructions,
• (3) Logical Instructions,
• (4) Branching Instructions,
• (5) Control Instructions,
 (1) Data Transfer Instructions

• MOV Rd, Rs
• MOV M, Rs
• MOV Rd, M
• This instruction copies the contents of the source
register into the destination register.
• The contents of the source register are not
altered.
• Example: MOV B,A or MOV M,B or MOV C,M
BEFORE EXECUTION AFTER EXECUTION

A 20 B 10 MOV B,A A 20 B 20

A F A F
B 30 C B 30 C
D E MOV M,B D E
H 20 L 50 H 20 L 50 30

A F A F
B C B C 40
D E MOV C,M
D E
H 20 L 50 40 H 20 L 50 40
 (2) Data Transfer Instructions

• MVI R, Data(8-bit)
• MVI M, Data(8-bit)

• The 8-bit immediate data is stored in the

destination register (R) or memory (M)
• R is general purpose 8 bit register such as
A,B,C,D,E,H and L.

• Example: MVI B, 60H or MVI M, 40H

 BEFORE EXECUTION AFTER EXECUTION

A F A F
B C B 60 C
D E MVI B,60H D E
H L H L

BEFORE EXECUTION AFTER EXECUTION

204FH 204FH
40
HL=2050H HL=2050H
MVI M,40H
2051H 2051H
 (3) Data Transfer Instructions

• LDA 16-bit address

• The contents of a memory location, specified

by a 16-bit address in the operand, are
copied to the accumulator (A).
• The contents of the source are not altered.

• Example: LDA 2000H

 BEFORE EXECUTION AFTER EXECUTION

A A 30

30 LDA 2000H 30
2000H 2000H
 (4) Data Transfer Instructions

• LDAX Register Pair

• Load accumulator (A) with the contents of
memory location whose address is specified
by BC or DE register pair.
• The contents of either the register pair or the
memory location are not altered.

• Example: LDAX D
 BEFORE EXECUTION AFTER EXECUTION

A F A 80 F

B C 80 B C 80
2030H 2030H
LDAX D
D 20 E 30 D 20 E 30
 (5) Data Transfer Instructions

• STA 16-bit address

• The contents of accumulator are copied into

the memory location i.e. address specified by
the operand in the instruction.

• Example: STA 2000 H

 BEFORE EXECUTION AFTER EXECUTION

A 50 A 50

50
2000H STA 2000H 2000H
 (6) Data Transfer Instructions

• STAX Register Pair

• Store the contents of accumulator (A) into

the memory location whose address is
specified by BC Or DE register pair.

• Example: STAX B
 BEFORE EXECUTION AFTER EXECUTION

A 50 F A 50 F

B 10 C 20 B 10 C 20 50

1020H 1020H
D E
STAX B D E
 (7) Data Transfer Instructions

• SHLD 16-bit address

• Store H-L register pair in memory.

• The contents of register L are stored into
memory location specified by the 16-bit address.
• The contents of register H are stored into the
next memory location.

• Example: SHLD 2500 H

 BEFORE EXECUTION AFTER EXECUTION

H 30 L 60 H 30 L 60

204FH 204FH

60
2500H SHLD 2500H 2500H

30
2502H 2501H
 (8) Data Transfer Instructions

• XCHG

• The contents of register H are exchanged

with the contents of register D.
• The contents of register L are exchanged with
the contents of register E.

• Example: XCHG
 BEFORE EXECUTION AFTER EXECUTION

D 20 E 40 D 70 E 80

H 70 L 80 XCHG H 20 L 40
 (9) Data Transfer Instructions

• SPHL

• Move data from H-L pair to the Stack Pointer

(SP)
• This instruction loads the contents of H-L pair
into SP.

• Example: SPHL
 BEFORE EXECUTION

SP
H 25 L 00

SPHL

AFTER EXECUTION

SP 2500
H 25 L 00
 (10) Data Transfer Instructions

• XTHL
• Exchange H–L with top of stack
• The contents of L register are exchanged with
the location pointed out by the contents of
the SP.
• The contents of H register are exchanged
with the next location (SP + 1).

• Example: XTHL
 L=SP
H=(SP+1)

BEFORE EXECUTION AFTER EXECUTION

SP 2700 50 SP 2700 40
2700H
2700H
H L H L
30 40 60 60 50 30
2701H 2701H
XTHL
2702H
2702H
 (11) Data Transfer Instructions

• PCHL

• Load program counter with H-L contents

• The contents of registers H and L are copied
into the program counter (PC).
• The contents of H are placed as the high-order
byte and the contents of L as the low-or byte.

• Example: PCHL
BEFORE EXECUTION AFTER EXECUTION

PC PC 6000

H
60
L
00 PCHL H
60
L
00
 (12) Data Transfer Instructions

• IN 8-bit port address

• Copy data to accumulator from a port with 8-

bit address.
• The contents of I/O port are copied into
accumulator.

• Example: IN 80 H
 BEFORE EXECUTION

PORT 80H 10 A

IN 80H

AFTER EXECUTION

PORT 80H 10 A 10
 (13) Data Transfer Instructions

• OUT 8-bit port address

• Copy data from accumulator to a port with 8-

bit address
• The contents of accumulator are copied into
the I/O port.

• Example: OUT 50 H
 BEFORE EXECUTION

PORT 50H 10 A 40

OUT 50H

AFTER EXECUTION

PORT 50H 40 A 40
 Arithmetic Instructions
• These instructions perform the operations
like:

• Addition
• Subtraction
• Increment
• Decrement
 (1) Arithmetic Instructions

• ADD R
• ADD M
• The contents of register or memory are added to
the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
 BEFORE EXECUTION AFTER EXECUTION

A 20 A 50

B C 30 B C 30
D E ADD C D E
H L
H L
A=A+R

BEFORE EXECUTION AFTER EXECUTION

A 20 ADD M A 30
B C B C
D E A=A+M D E
H 20 L 50 10 H 20 L 50 10

2050 2050
 (2) Arithmetic Instructions

• ADC R
• ADC M
• The contents of register or memory and Carry Flag (CY) are
added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified
by H-L pair. All flags are modified to reflect the result of the
addition.

• Example: ADC C or ADC M

 BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0

A 50 A 71
B C 20 B C 20
D E
ADC C D E
H L
A=A+R+CY H L

BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0

A 20 2050H 30 ADC M A 51 2050H 30

A=A+M+CY
H 20 L 50 H 20 L 50
 (3) Arithmetic Instructions

• ADI 8-bit data

• The 8-bit data is added to the contents of

accumulator.
• The result is stored in accumulator.

• Example: ADI 10 H
BEFORE EXECUTION AFTER EXECUTION

A 50 A 60

ADI 10H
A=A+DATA(8)
 (4) Arithmetic Instructions

• ACI 8-bit data

• The 8-bit data and the Carry Flag (CY) are

added to the contents of accumulator.
• The result is stored in accumulator.

• Example: ACI 20 H
BEFORE EXECUTION AFTER EXECUTION

CY 1
ACI 20H CY 0

A=A+DATA
A 30 A 51

(8)+CY
 (5) Arithmetic Instructions

• DAD Register pair

• The 16-bit contents of the register pair are

added to the contents of H-L pair.
• The result is stored in H-L pair.
• If the result is larger than 16 bits, then CY is
set.

• Example: DAD D
BEFORE EXECUTION AFTER EXECUTION

CY 0 CY 0

SP SP
B
D 10
C
E 20
DAD D B
D 10
C
E 20
H 20 L 50 HL=HL+R H 30 L 70
 (6) Arithmetic Instructions

• SUB R
• SUB M
• The contents of the register or memory location are
subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.

• Example: SUB B or SUB M

 BEFORE EXECUTION AFTER EXECUTION

A 50 A 20
B 30 C B 30 C
D E SUB B D E
H L
A=A-R H L

BEFORE EXECUTION AFTER EXECUTION

10
A 50
1020H A 40 1020H
10

H L SUB M H L
10 20
A=A-M 10 20
 (7) Arithmetic Instructions

• SBB R
• SBB M
• The contents of the register or memory location and Borrow Flag
(i.e.CY) are subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified by H-L
pair.

• Example: SBB C or SBB M

 BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0

A 40 A 1F
B C 20 SBB C B C 20
D E A=A-R-CY D E
H L H L

BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0
10 10
A 50 2050H A 3F 2050H
H L
SBB M H L
20 50 A=A-M-CY 20 50
 (8) Arithmetic Instructions

• SUI 8-bit data

• OPERATION: A=A-DATA(8)
• The 8-bit immediate data is subtracted from
the contents of the accumulator.
• The result is stored in accumulator.

• Example: SUI 45 H
 (9) Arithmetic Instructions

• SBI 8-bit data

• The 8-bit data and the Borrow Flag (i.e. CY) is

subtracted from the contents of the
accumulator.
• The result is stored in accumulator.

• Example: SBI 20 H
BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0

A 50 SBI 20H A 2F

A=A-DATA(8)-CY
 (10) Arithmetic Instructions

• INR R
• INR M
• The contents of register or memory location are
incremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address is
specified by the contents of H-L pair.

• Example: INR B or INR M

 BEFORE EXECUTION AFTER EXECUTION

A A
B 10 C INR B B 11 C
D
H
E
L
R=R+1 D
H
E
L

BEFORE EXECUTION AFTER EXECUTION

H L 30 H L 31
20 50 2050H 20 50 2050H
INR M
M=M+1
 (11) Arithmetic Instructions

• INX Rp

• The contents of register pair are incremented

by 1.
• The result is stored in the same place.

• Example: INX H
 (12) Arithmetic Instructions

• DCR R
• DCR M
• The contents of register or memory location are
decremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
• Example: DCR E or DCR M
 BEFORE EXECUTION AFTER EXECUTION

A A
B C B C
D E 20 DCR E D E 1F
H L
R=R-1 H L

BEFORE EXECUTION AFTER EXECUTION

H L
H L 21 20 50 20
2050H
20 50 2050H
DCR M
M=M-1
 (13) Arithmetic Instructions

• DCX Rp

• The contents of register pair are decremented

by 1.
• The result is stored in the same place.

• Example: DCX D
BEFORE EXECUTION AFTER EXECUTION

SP SP

B C B C
D 10 E 20 DCX D D
H
10 E
L
1F
H L
RP=RP-1
 (1) Logical Instructions

• ANA R
• ANA M

• AND specified data in register or memory with

accumulator.
• Store the result in accumulator (A).

• Example: ANA B, ANA M

 BEFORE EXECUTION 1010 1010=AAH AFTER EXECUTION
0000 1111=0FH
CY AC CY 0 AC 1
0000 1010=0AH
A AA A 0A
B 10
0F C B 0F C
ANA B
D E D E
A=A and R
H L H L

BEFORE EXECUTION AFTER EXECUTION

0101 0101=55H
CY AC 1011 0011=B3H CY 0 AC 1

B3 0001 0001=11H B3
A 55 A 11 2050H
2050H
H 20 L 50 H 20 L 50
ANA M
A=A and M
 (2) Logical Instructions

• ANI 8-bit data

• AND 8-bit data with accumulator (A).

• Store the result in accumulator (A)

• Example: ANI 3FH

BEFORE EXECUTION AFTER EXECUTION

1011 0011=B3H
0011 1111=3FH

0011 0011=33H

CY AC CY 0 AC 1
ANI 3FH
A B3 A=A and DATA(8) A 33
 (3) Logical Instructions

• XRA Register (8-bit)

• XOR specified register with accumulator.

• Store the result in accumulator.

• Example: XRA C
 1010 1010=AAH
BEFORE EXECUTION 0010 1101=2DH AFTER EXECUTION

1000 0111=87H

CY AC CY 0 AC 0

A AA A 87
B 10 C 2D B C 2D
D E XRA C D E
H L
A=A xor R H L
 (4) Logical Instructions

• XRA M

• XOR data in memory (memory location

pointed by H-L pair) with Accumulator.
• Store the result in Accumulator.

• Example: XRA M
 0101 0101=55H
BEFORE EXECUTION 1011 0011=B3H AFTER EXECUTION
1110 0110=E6H

CY AC CY 0 AC 0
B3 XRA M B3
A 55 2050H A E6 2050H
A=A xor M
H 20 L 50 H 20 L 50
 (5) Logical Instructions

• XRI 8-bit data

• XOR 8-bit immediate data with accumulator (A).

• Store the result in accumulator.

• Example: XRI 39H

 1011 0011=B3H
0011 1001=39H

BEFORE EXECUTION 1000 1010=8AH AFTER EXECUTION

CY AC CY 0 AC 0
XRI 39H
A B3 A=A xor DATA(8) A 8A
 (6) Logical Instructions

• ORA Register

• OR specified register with accumulator (A).

• Store the result in accumulator.

• Example: ORA B
 1010 1010=AAH
0001 0010=12H
BEFORE EXECUTION AFTER EXECUTION
1011 1010=BAH

CY AC CY 0 AC 0

ORA B
A=A or R
A AA A BA
B 12 C B 12 C
D E D E
H L H L
 (7) Logical Instructions

• ORA M

• OR specified register with accumulator (A).

• Store the result in accumulator.

• Example: ORA M
 0101 0101=55H
1011 0011=B3H
BEFORE EXECUTION AFTER EXECUTION
1111 0111=F7H

CY AC CY 0 AC 0

ORA M
B3
A=A or M
B3
A 55 2050H A F7 2050H
H 20 L 50 H 20 L 50
 (8) Logical Instructions

• ORI 8-bit data

• OR 8-bit data with accumulator (A).

• Store the result in accumulator.

• Example: ORI 08H

 1011 0011=B3H
0000 1000=08H

BEFORE EXECUTION 1011 1011=BBH AFTER EXECUTION

CY AC CY 0 AC 0
ORI 08H
A B3 A=A or DATA(8) A BB
 (9) Logical Instructions

• CMP Register
• CMP M

• Compare specified data in register or memory with

accumulator (A).
• Flags are affected.
 BEFORE EXECUTION A>R: CY=0,Z=0 AFTER EXECUTION
A=R: CY=0,Z=1
CY Z A<R: CY=1,Z=0 CY 0 Z 0

A B8 A B8
B 10 C B C
CMP D
D B9 E D B9 E
A-R
H L H L

BEFORE EXECUTION AFTER EXECUTION

A>M: CY=0,Z=0
A=M: CY=0,Z=1
A<M: CY=1,Z=0
CY Z CY 0 Z 1

B8 B8
A B8 2050H A B8 2050H
CMP M
H 20 L 50 A-M H 20 L 50
 (10) Logical Instructions

• CPI 8-bit data

• Compare 8-bit immediate data with

accumulator (A).
• Flags are affected.

• Example: CPI 30H

 A>DATA: CY=0,Z=0
A=DATA: CY=0,Z=1
BEFORE EXECUTION A<DATA: CY=1,Z=0 AFTER EXECUTION

CY Z CY 0 AC 0
CPI 30H
A-DATA
A BA A BA

1011 1010=BAH
 (11) Logical Instructions

• STC

• It sets the carry flag to 1.

• Example: STC
BEFORE EXECUTION AFTER EXECUTION

CY 0 CY 1

STC
CY=1
 (12) Logical Instructions

• CMC

• It complements the carry flag.

• Example: CMC
BEFORE EXECUTION AFTER EXECUTION

CY 1 CY 0

CMC
 (13) Logical Instructions

• CMA

• It complements each bit of the accumulator.

• Example: CMA
 (14) Logical Instructions

• RLC
• Rotate accumulator left
• Each binary bit of the accumulator is rotated left
by one position.
• Bit D7 is placed in the position of D0 as well as in
the Carry flag.
• CY is modified according to bit D7.

• Example: RLC.
 BEFORE EXECUTION

CY B7 B6 B5 B4 B3 B2 B1 B0

AFTER EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 B7
 (15) Logical Instructions

• RRC
• Rotate accumulator right
• Each binary bit of the accumulator is rotated right by
one
• position.
• Bit D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.

• Example: RRC.
 BEFORE EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 CY

AFTER EXECUTION

B0 B7 B6 B5 B4 B3 B2 B1 B0
 (16) Logical Instructions

• RAL
• Rotate accumulator left through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.

• Example: RAL.
 BEFORE EXECUTION

CY B7 B6 B5 B4 B3 B2 B1 B0

AFTER EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 CY
 (17) Logical Instructions

• RAR
• Rotate accumulator right through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry flag
is placed in the least significant position D0.
• CY is modified according to bit D7.

• Example: RAR
 BEFORE EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 CY

AFTER EXECUTION

CY B7 B6 B5 B4 B3 B2 B1 B0
 Concept of Subroutine
• In 8085 microprocessor a subroutine is a
separate program written aside from main
program ,this program is basically the
program which requires to be executed
several times in the main program.
• The microprocessor can call subroutine any
time using CALL instruction. after the
subroutine is executed the subroutine hands
over the program to main program using RET
instruction.
 Branching Instructions

• The branch group instructions allows the

microprocessor to change the sequence of
program either conditionally or under certain
test conditions. The group includes,
• (1) Jump instructions,
• (2) Call and Return instructions,
• (3) Restart instructions,
 (1) Branching Instructions
• JUMP ADDRESS
• BEFORE EXECUTION AFTER EXECUTION
PC PC 2000
JMP 2000H

• Jump unconditionally to the address.

• The instruction loads the PC with the address
given within the instruction and resumes the
program execution from specified location.
• Example: JMP 200H
 Conditional Jumps
Instruction Code Decription Condition For Jump

JC Jump on carry CY=1

JNC Jump on not carry CY=0

JP Jump on positive S=0

JM Jump on minus S=1

JPE Jump on parity even P=1

JPO Jump on parity odd P=0

JZ Jump on zero Z=1

JNZ Jump on not zero Z=0

 (2) Branching Instructions
• CALL address

• Call unconditionally a subroutine whose

starting address given within the
instruction and used to transfer program
control to a subprogram or subroutine.

• Example: CALL 2000H

 Conditional Calls
Instruction Code Description Condition for CALL

CC Call on carry CY=1

CNC Call on not carry CY=0

CP Call on positive S=0

CM Call on minus S=1

CPE Call on parity even P=1

CPO Call on parity odd P=0

CZ Call on zero Z=1

CNZ Call on not zero Z=0

 (3) Branching Instructions
• RET

• Return from the subroutine unconditionally.

• This instruction takes return address from
the stack and loads the program counter with
this address.

• Example: RET
 BEFORE EXECUTION AFTER EXECUTION

SP 27FD 00 SP 27FF 00
27FDH 27FDH
PC PC 6200
62 62
27FEH 27FEH
RET
27FFH 27FFH
 (4) Branching Instructions
• RST n

• Restart n (0 to 7)
• This instruction transfers the program control
to a specific memory address. The processor
multiplies the RST number by 8 to calculate
the vector address.

• Example: RST 6
Vector Address For Return Instructions
Instruction Code Vector Address

RST 0 0*8=0000H

RST 1 0*8=0008H

RST 2 0*8=0010H

RST 3 0*8=0018H

RST 4 0*8=0020H

RST 5 0*8=0028H

RST 6 0*8=0030H

Rst 7 0*8=0038H
 (1) Control Instructions
• NOP

• No operation
• No operation is performed.
• The instruction is fetched and decoded but no
operation is executed.

• Example: NOP
 (2) Control Instructions
• HLT

• Halt
• The CPU finishes executing the current instruction
and halts any further execution.
• An interrupt or reset is necessary to exit from the
halt state.

• Example: HLT
 (3) Control Instructions
• RIM

• Read Interrupt Mask

• This is a multipurpose instruction used to read the status
of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
• The instruction loads eight bits in the accumulator with
the following interpretations.

• Example: RIM
RIM INSTRUCTION
• SIM

• Set Interrupt Mask

• This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
• The instruction interprets the accumulator contents as
follows.

• Example: SIM
SIM Instruction
 END OF
INSTRUCTION SET
 Microprocessor understands Machine Language only!

• Microprocessor cannot understand a program

written in Assembly language
• A program known as Assembler is used to convert a
Assembly language program to machine language

Assembly Machine
Assembler
Language Language
Program
Program Code
 Low-level/High-level languages
• Machine language and Assembly language are both
– Microprocessor specific (Machine dependent)
so they are called
– Low-level languages
• Machine independent languages are called
– High-level languages
– For e.g. BASIC, PASCAL,C++,C,JAVA, etc.
– A software called Compiler is required to convert
a high-level language program to machine code
2. Programming model of 8085

Accumulator 16-bit
Address Bus
Register Array
ALU

Memory Pointer
Flags Registers 8-bit Data
Bus
Instruction
Decoder

Control Bus
Timing and Control Unit
Accumulator (8-bit) Flag Register (8-bit)
S Z AC P CY

B (8-bit) C (8-bit)
D (8-bit) E (8-bit)
H (8-bit) L (8-bit)
Stack Pointer (SP) (16-bit)
Program Counter (PC) (16-bit)

8- Lines 16- Lines

Bidirectional Unidirectional
Overview: 8085 Programming model

1. Six general-purpose Registers

2. Accumulator Register
3. Flag Register
4. Program Counter Register
5. Stack Pointer Register
 Writing a Assembly Language Program

• Steps to write a program

– Analyze the problem
– Develop program Logic
– Write an Algorithm
– Make a Flowchart
– Write program Instructions using
Assembly language of 8085
Program 8085 in Assembly language to add two 8-
bit numbers and store 8-bit result in register C.

1. Analyze the problem

– Addition of two 8-bit numbers to be done
2. Program Logic
– Add two numbers
– Store result in register C
– Example
10011001 (99H) A
+00111001 (39H) D
11010010 (D2H) C
 Translation to 8085
3. Algorithm
operations
1. Get two numbers • Load 1st no. in register D
• Load 2nd no. in register E
2. Add them • Copy register D to A
• Add register E to A

3. Store result • Copy A to register C

4. Stop • Stop processing

 4. Make a Flowchart
Start
• Load 1st no. in register D
Load Registers D, E • Load 2nd no. in register E

Copy D to A • Copy register D to A

• Add register E to A
Add A and E

Copy A to C
• Copy A to register C

• Stop processing
Stop
5. Assembly Language Program
1. Get two numbers
a) Load 1st no. in register D MVI D, 2H
b) Load 2nd no. in register E MVI E, 3H
2. Add them
a) Copy register D to A MOV A, D
b) Add register E to A ADD E
3. Store result
a) Copy A to register C MOV C, A
4. Stop
a) Stop processing HLT
Program 8085 in Assembly language to add two 8-
bit numbers. Result can be more than 8-bits.

1. Analyze the problem

– Result of addition of two 8-bit numbers can
be 9-bit
– Example
10011001 (99H) A
+10011001 (99H) B
100110010 (132H)
– The 9th bit in the result is called CARRY bit.
• How 8085 does it?
– Adds register A and B
– Stores 8-bit result in A
– SETS carry flag (CY) to indicate carry bit

10011001 99H A
+
10011001 99H B

1
0 00110010
1001100 32H
99H A
1
CY
• Storing result in Register memory
CY A
1 10011001 32H

Register B Register C

Step-1 Copy A to
C Step-2
a) Clear register B
b) Increment B by
1
 2. Program Logic

1. Add two numbers

2. Copy 8-bit result in A to C
3. If CARRY is generated
– Handle it
4. Result is in register pair BC
 3. Algorithm Translation to 8085
operations
1. Load two numbers • Load registers D, E
in registers D, E
• Copy register D to A
2. Add them
• Add register E to A
•• Copy
Copy A
A to
to register
register C
C
3. Store 8 bit result in
C • Use Conditional
4. Check CARRY flag Jump instructions
5. If CARRY flag is
• Clear register B
SET
• Store CARRY in • Increment B
register B • Stop processing
6. Stop
 4. Make a Flowchart
Start

Load Registers D, E If False

CARRY Clear B
NOT SET
Copy D to A
Increment B
Tru
Add A and E e

Copy A to C
Stop
5. Assembly Language Program
• Load registers D, E MVI D, 2H
MVI E, 3H
• Copy register D to A
• Add register E to A MOV A, D
•• Copy
Copy A
A to
to register
register C
C ADD E
MOV C, A
• Use Conditional
JNC END
Jump instructions
• Clear register B MVI B, 0H
• Increment B INR B
• Stop processing END: HLT
8 bit ADDITION
136
8 bit Subtraction

137
138
 PROGRAM FOR SUBTRACTION OF TWO 8
BIT DATA
LDA 4201
MOV B,A
LDA 4200
MVI C,00
SUB B
JNC AHEAD
INR C
CMA
ADI 01
AHEAD: STA 4202
MOV A,C
STA 4203
HLT
 MULTIPLICATION OF TWO 8 BIT DATA
LXI H,4200
MVI C,00
XRA A
MOV B,M
INX H
MOV D,M
REPEAT: ADD D
JNC AHEAD
INR C
AHEAD: DCR B
JNZ REPEAT
INX H
MOV M,A
INX H
MOV M,C
HLT
DIVISION OF TWO 8 BIT NUMBERS
LDA 4201
MOV B,A
LDA 4200
MVI C,00
AGAIN: CMP B
JC STORE
SUB B
INR C
JMP AGAIN
STORE: STA 4203
MOV A,C
STA 4202
HLT
PROGRAM TO FIND SMALLEST OF GIVEN ‘N’
NUMBERS
LXI H,4200H
MOV B,M
INX H
MOV A,M
DCR B
LOOP : INX H
CMP M
JC AHEAD
MOV A,M
AHEAD: DCR B
JNZ LOOP
STA 4300H
HLT
 PROGRAM TO FIND LARGEST OF GIVEN ‘N’
NUMBERS
LXI H,4200H
MOV B,M
INX H
MOV A,M
DCR B
LOOP : INX H
CMP M
JNC AHEAD
MOV A,M
AHEAD: DCR B
JNZ LOOP
STA 4300H
HLT
 SORT IN ASCENDING ORDER
LDA 4200H
MOV B,A
DCR B
LOOP2: LXI H,4200H
MOV C,M
DCR C
INX H
LOOP 2 : MOV A,M
INX H
CMP M
JC AHEAD
MOV D,M
MOV M,A
DCX H
MOV M,D
INX H
AHEAD: DCR C
JNZ LOOP1
DCR B
JNZ LOOP2
HLT
 SORT IN DESCENDING ORDER
LDA 4200H
MOV B,A
DCR B
LOOP2: LXI H,4200H
MOV C,M
DCR C
INX H
LOOP 2 : MOV A,M
INX H
CMP M
JNC AHEAD
MOV D,M
MOV M,A
DCX H
MOV M,D
INX H
AHEAD: DCR C
JNZ LOOP1
DCR B
JNZ LOOP2
HLT
HEXA TO ASCII CODE CONVERSION
LDA 4200H
MOV B,A
ANI 0FH
CALL ACODE
STA 4201H
MOV A,B
ANI FOH
RLC
RLC
RLC
RLC
CALL ACODE
STA 4202H
HLT
SUBROUTINE PROGRAM FOR HEXA TO
ASCII CODE CONVERSION
ACODE: CPI OAH
JC SKIP
ADI 07H
SKIP:ADI 30H
RET
ASCII TO HEX CODE CONVERSION
LXI H,4200H
MOV D,M
LXI B,4300H
LOOP: INX H
MOV A,M
CALL HEX
STAX B
INX B
DCR D
JNZ LOOP
HLT
SUBROUTINE PROGRAM FOR HEXA TO
ASCII CODE CONVERSION
HEX: SUI 30H
CPI 0AH
RC
SUI 07H
RET
Looping, indexing and counting
• Looping in 8085
• Looping is a programming technique that
instructs the Microprocessor to repeat tasks. It
is accomplished by changing the sequence of
execution using jump instructions.
• Loops can be classified into two groups:
• Continous Loops.
• Conditional Loops.
 • Continous Loops
A continuous loops repeats a task continuously. It is
setup by using unconditional jump instruction. A
program with a continuous loop will keep repeating tasks
until the system is reset .
• Conditional Loops
A conditional loop repeat a task if some conditions
are satisfied. They are setup by conditional jump
instructions. These instructions check flags(Z, CY, P, S)
and repeat the tasks based on the flag Status. These
loops include counting and indexing.
Conditional Loop and Counter
• A counter is a typical application of the conditional
loop. To achieve the looping task, the microprocessor
requires a counter and a flag. A counter is set up by
loading a suitable count into a register.
• Counting is accomplished by either incrementing or
decrementing the counter.
• A conditional jump instruction creates the loop and
the end of counting is indicated by a flag.
• Indexing
Pointing objects with sequential numbers is
called indexing. Data bytes are stored in
memory locations and are referred to by their
memory locations.
 Delay Generation in 8085
• The counting method described above has a significant
downside in that it is performed at such a high speed that
only the final count can be seen. So to notice the counting,
there must be an appropriate time delay between counts.
• Depending on the time delay required, a register is loaded
with a number, and then the register is decremented until
it reaches zero by setting up a loop with a conditional jump
instruction. The delay is caused by the loop, which is
determined by the system’s clock period.
 The following methods are used for generating
delays:
• Using NOP instructions.
• Using 8-bit register as counter.
• Using 16-bit register pair as counter.
• Using NOP Instructions
One of the most common applications of the NOP
instruction is in the generation of delays. The NOP
instruction requires four clock pulses to fetch,
decode, and execute. As a result, this form of NOP
instruction can be used to induce a few milliseconds
of time delay.
 Time Delay Using One Register
• The following program will demonstrate the time delay using
8-bit counter.
MVI B, FFH
LOOP: DCR B
JNZ LOOP
RET
• The first instruction will be executed once, which will take 7
T-states. The DCR C instruction requires 4 T-states. This will
be executed 255 (FF) times. The JNZ instruction takes 10 T-
states when it jumps (It jumps 254 times), otherwise it will
take 7 T-States. The RET instruction requires 10 T-States.
 Time Delay Using a Register Pair

• Instead of an 8-bit counter, we can do the same task with a

16-bit register pair. More time delay can be generated using
this method. For example:
LXI B,FFFFH
LOOP: DCX B
MOV A,B
ORA C
JNZ LOOP
RET
• This method can be used to get more than 0.5 seconds
delay.
 TIME DELAY LOOPS
Calculation of time delay using one register:
MVI B,80-------- 7 T
LOOP: DCR B----5 T
JNZ LOOP---------10 T
Assuming clock as 5MHZ
Number of T states for execution of LOOP is:
= (T states for DCR B+T states for JNZ)* Number of
times loop is executed
= (10+5)*128 T states
The delay time to execute LOOP instruction is
TL = T*Number of T states for execution of LOOP.
TL = 1/5*10-6(5+10)*128s = 384μs
Total time delay =TD = T0L+TL
= 1/5*10-6 *7+ 384μs = 385.4 μs
Using only one register a limited time delay is
generated. If very high time delay is required a
register pair will be used in place of a register.
 Calculation of Time Delay using Register
Pair
LXI D,8000 --------10 T
LOOP: DCX D ---------------5 T
MOV A,E --------------5 T
ORA D -------------------4 T
JNZ LOOP--------------10 T
The delay time to execute LOOP instruction is
TL = T*Number of T states for execution of LOOP.
TL = 1/5*10-6(5+5+4+10)*32768 = 157.268μs
Total time delay =TD = T0L+TL
= 1/5*10-6 *10+ 157.268 μs =157.288μs
 Timing
Diagram of
8085
Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.

Instruction Cycle:
The time required to execute an instruction
.

Machine Cycle:
The time required to access the memory
or input/output devices or acknowledging an
external request
T-State:
• The machine cycle and instruction cycle
takes multiple clock periods.
• A portion of an operation carried out in
one system clock period is called as T-
state.
 Timing diagrams
• The 8085 microprocessor has 7 basic machine
cycle. They are
1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
7. Bus idle cycle
Control and Status Signals.
1.Opcode fetch cycle(4T or 6T)
 OPCODE FETCH
• The Opcode fetch cycle, fetches the instructions from memory
and delivers it to the instruction register of the microprocessor
• Opcode fetch machine cycle consists of 4 T-states.
T1 State:
During the T1 state, the contents of the program counter are
placed on the 16 bit address bus. The higher order 8 bits are
transferred to address bus (A8-A15) and lower order 8 bits are
transferred to multiplexed A/D (AD0-AD7) bus.
ALE (address latch enable) signal goes high. As soon as
ALE goes high, the memory latches the AD0-AD7 bus. At
the middle of the T state the ALE goes low
T2 State:
During the beginning of this state, the RD’ signal goes low
to enable memory. It is during this state, the selected memory
location is placed on D0-D7 of the Address/Data multiplexed
bus.
T3 State:
In the previous state the Opcode is placed in D0-D7 of the
A/D bus. In this state of the cycle, the Opcode of the A/D
bus is transferred to the instruction register of the
microprocessor. Now the RD’ goes high after this action and
thus disables the memory from A/D bus.
T4 State:
In this state the Opcode which was fetched from the memory
is decoded.
2. Memory read cycle (3T)
• These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=1, S0=0. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. RD’ goes LOW
T3 State:
• The data which was loaded on the previous state is transferred
to the microprocessor. In the middle of the T3 state RD’ goes
high and disables the memory read operation. The data which
was obtained from the memory is then decoded. 136
3. Memory write
cycle (3T)
• These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=0, S0=1. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. WR’ goes LOW
T3 State:
• In the middle of the T3 state WR’ goes high and disables the
memory write operation. The data which was obtained from
the memory is then decoded.
4.I/O read
cycle(3T)
5.I/O write
cycle(3T)
STA instruction
ex: STA 526A
It require 4 m/c cycles
13 T states
1.opcode fetch(4T)
2.memory read(3T)
3.memory read(3T)
4.Memory write(3T)
 Timing diagram for
IN C0H
• Fetching the Opcode DBH from the memory
4125H.
• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to
the accumulator.
• Let the content of port is 5EH.
It require 3 m/c cycles
10 T states

opcode fetch(4T)
memory read(3T)
I/O read(3T)

145
 OUT
instruction
Machines Cycles(10T):
1.instruction fetch(4T)
2.memory read (3T)
3.IO write (3T)
Address Hex Codes Mnemonic Comment

2000 D3 OUT F0H Accumulator content will be sent to port addressF0H

2001 F0 F0H as port address

 OUT INSTRUCTION
• Fetching the Opcode D3H from the memory
2000H.
• Read the port address F0H from 2001H.
• Read the content of port F0H and send it to
the accumulator.
• 5It require 3 m/c cycles 10 T states
• 1.instruction fetch(4T) 2.memory read (3T)
3.IO write (3T)
 Timing diagram for
• Fetching the MVI B, from
Opcode 06H 43 the memory
h

2000H. (OF machine cycle)

• Read (move) the data 43H from memory
2001H. (memory read)
INR M
ADD M
END OF UNIT II