ECE 124a/256c

VLSI RC(L) Interconnect Models

Forrest Brewer
Wayne Burleson, Atul Maheshwari
 Readings
 H. B. Bakoglu, “Circuits interconnects and packaging for
VLSI ” , Addison Wesley
 W. J. Dally and J. W. Poulton, “Digital Systems Engineering”
, Cambridge Press
 J. M. Rabaey, “Digital Integrated circuits : A design
perspective” , Prentice Hall
 Components of VLSI system
 Logic
 Functional Block
 Logic Gates
 Transistors
Router Logic
 Interconnects
Cache Tags
 Power/ground and Clock L2 L2
 Inter-block Signals Cache Cache
 Intra-block Signals
Processor
Core
Delay with technology scaling

This figure is from the ITRS Roadmap on interconnects

 NTRS Roadmap

Year
2003 2004 2005 2008 2011 2014
Parameter

Technology(nm) 120 110 100 70 50 35

# of Transistors 95.2M 145M 190M 539M 1523M 4308M

Clock Frequency 1724 MHz 1857 MHz 2000 MHz 2500 MHz 3000 MHz 3600 MHz

Chip Area (mm2) 372 372 408 468 536 615

Wiring Levels 8 8 8-9 9 9-10 10

Pitch(L/I/G)(nm) 330/420/690 295/375/620 265/340/560 185/240/390 130/165/275 95/115/190

A/R (L/I/G) 1.6/2.2/2.8 1.6/2.3/2.8 1.7/2.4/2.8 1.9/2.5/2.9 2.1/2.7/3.0 2.3/2.9/3.1

Dielectric Const. 2.2-2.7 2.2-2.7 1.6-2.2 1.5 <1.5 <1.5

This data is from the ITRS Roadmap on interconnects

 Interconnect dimension trends in
terms of IC generations

These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001
 Rent’s rule
 Rent’s rule relates the I/O requirement to the number of
gates as :

N p K p N g
 As technology scales number of gates in a given area is
increasing.
 More routing is required as technology scales.
 Nature of the interconnect

Number of wires
1000
Donath
Local Interconnect Occupation prob.
100
Measurement

10
Global Interconnect
1

0.1
1 10 100
Wire length

These figures are derived from Digital integrated circuit – a design perspective, J. Rabaey Prentice Hall and a tutorial in SLIP by Dirk Stroobandt respectively
 Microprocessor Interconnect

Local Interconnect Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
(Log Scale)
No of nets

SGlobal = SDie
SLocal = STechnology

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
VLSI Design Cycle

Chip Specs Synthesis Extraction

Timing Timing
Partitioning
Analysis Analysis

Floorplan
Timing met Timing met
RTL

Layou Chip Tape out

t
 Early models
 Wire width  feature size
 Older technology had wide wires
 More cross-section area implies less resistance and more
capacitance.
 Model wire only with capacitance

L 
H
W
 However…
 With scaling, width of wire reduced.
 Resistance of the wire no longer negligible.
 Wire not very long and a lumped RC is good enough
approximation.

L 
H
W
 Interconnect Resistance

L
L R
H
HW
W
 Ohm’s Law: Resistance of wire  wire length (L) and 1/
cross-section(HW)
  (resistivity) is the property of the material.
Sheet Resistance

 Wire height (H) is constant for a technology.

 Sheet resistance (Rq) is constant for each
metal layer.
 Calculation of wire resistance is easy : multiply Rq by
L/W L
R Rq
W
with

Rq 
H
 Interconnect Capacitance
 Capacitance of a wire = f (Shape, Distance to
surrounding wires, Distance to the substrate )
 Estimating Capacitance is a matter of determining
where the field lines go.
 To get an accurate estimate electric field solvers (2D or
3D) are used. E.g. Fastcap or Rafael
 When in doubt, typical wires have self capacitance
between 1 and 3 pf/cm
 Area Capacitance

Current

W
L

tdi Dielectric

Substrate
Electric
Fields

 di
Cint  WL
t di
Fringing Capacitance
H w
Fringing Fields

Conductor

+


2 di w di
C wire C pp  C fringe  
log(t di / H ) t di
w  W-H/2
 Detailed Picture

Is this much of detail required… How to

compute this?
Interwire Capacitance

(from [Bakoglu89])
 Wiring Capacitances (0.18m)
Capacitance N+ P+ poly m1 m2 m3 m4 m5 m6

substrate 998+244 1152+201 103+21 39+38 19+61 13+55 9+43 8+25 3

N+ active 8655 54 21 14 11 10 9

P+ active 8324

poly 64+69 18+39 10+29 7+24 6+21 5+19

m1 44+61 16+35 10+31 7+23 5+21

m2 38+54 15+37 9+27 7+24

m3 40+56 15+34 9+31

m4 37+58 14+40

m5 36+61

Units: First number is area component (af/m2), second is fringing component (af/m)
 How to use fringe capacitance
tables
 Estimation of wire Capacitance
 Where do field lines terminate?
 What fraction go where?
 E.g. 1cm of M1 over substrate:39af/m2, 38af/m fringe
 If 200nm wide = 0.2um, 0.2um*10,000um=2,000*39af=78fF
 1cm = 10,000um, fringe on both sides: 2*38af*10,000 = 760fF
 Total = 848fF/cm
 Over Poly 64aF, 69aF – nearly doubles (half the distance to
conductor)
 Importance of Resistance
 Delay of wire  to the resistance of the wire.
 Resistance means ohmic (IR) drop along the wire, reduces
noise margin.
 IR drop a significant problem in the power lines where
current density if high.
 Keep wires short, to reduce resistance.
 Contact resistance makes them vulnerable to
electromigration.
Metal Resistivity
 Importance of capacitance
 Delay of the wire is proportional to the capacitance charged.
 More capacitance means more dynamic power.
 Capacitance an increasing source of noise (coupling).
 Coupling make delay estimation hard.
Distributed model

 Wire can be modeled as a distributed RC line.

 As the number of elements increase distributed model

becomes more accurate.
 For practical purposes wire-models with 5-10 elements
are used to model the wire.
 Elmore Delay…
 First order time constant at node is a sum of RC
components.
 All the upstream resistances are taken into account.
 Thus each node contributes to the delay.
 Amount of contribution is the product of the cap at the node
and the amount of resistance from source to the node.
 Delay in distributed RC line
 Elmore analyzed the distributed model and came up with the
figures for delay.

R1 R2 Ri-1 Ri RN-1 RN
Vin 1 2 i-1 i N-1 N
Vout
C C Ci-1 Ci CN-1 CN
1 2

N N N i
 N  Ri  C j  Ci  R j
i 1 j i i 1 j 1

Elmore derived this equation in 1948 way before VLSI !!!

Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

 Generalized Elmore delay

Rubinstein, Penfield and Horowitz generalized Elmore delay

This figure is derived from Digital integrated circuit – a design perspective, J. Rabaey Prentice Hall
Step-response of RC wire as a
function of time and space
2.5

x= L/10
2

x = L/4
1.5
voltage (V)

x = L/2
1
x= L

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)
 RC and flight-time

for a wide bus above a plane and beneath orthogonally routed layer
These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001
 Pi Model
R/3 R/3 R/3

 Pi Model of wire: C/2 C/2

 Elmore Delay = RC/3+RC/6 = RC/2 agrees with distributed

model RC
 Pi Model is often used in Spice instead of large number of
segments as a reasonable approximation of distributed RC
 Driving an RC-line

Rs
(r w,cw,L)
Vo ut

Vi n

 Delay for FET driven distributed RC – Rs is equivalent source

resistance (usually assumed Rs = Vdd/(2 Isat))
 RC gives delay for exp(-1) change in output
 Scale time by ln(2) = 0.69 to get typical 50% CMOS gate
threshold
 Repeaters

 Repeaters are buffers or inverters inserted at regular

intervals.
 Delay linearly proportional to the wire length
 Questions to be answered – Where and how big should the
repeaters be ?
 Repeater placement
 Delay of the interconnect is typically optimum when
Delaywire = Delaybuffer
 Closed form solutions for Repeater Number and Sizing

Bakoglu and Meindl, 1985 (Classical)

Adler and Friedman, 1998 (considering inductance)

Nalamalpu and Burleson, 2000 (ramped waveforms)

Chen Marek-Sadowska, Brewer, 2003 (short channel timing)

Cong, 2004 (tapered wires)
 Bakoglu and Meindl Model

 For a wire with k repeaters each of size h times minimum size inverter
is given by:
Ro Rint, Cint

Co

 Ro  Cint  Rint  Cint 

T50% k  0.7   hCo    0.4  0.7 hCo  
 h  k  k  k 
 Bakoglu and Meindl…
 By setting dT/dk = 0 and dT/dh = 0, optimal values for k and h are
obtained

0.4 Rint Cint RoCint

k h
0.7 RoCo Rint Co
 Substituting these back, delay is given by

T50% 2.5 RoCo Rint Cint

 Optimization: Lagrange
Multipliers
 A general technique for multi-dimensional optimization
 Problem: A function f(x1, x2, …, xn) to maximize subject to
several constraints: g1(x1, x2, …, xn) = 0, g2(x1, x2, …, xn)=0,
…, gm(x1, x2, …,xn) = 0 where m<n.
f 1g1   2g 2  ...   mg m
 Solution:

 The n-dimensional equation above plus the m constraints

provide n+m equations in n+m variables (xi’s and j’s)
 Note: it is often useful to examine the functional forms of the
lambdas – they are usually interesting.
Best Placement for repeaters

Clat -Clat

Clat
-Clat

Staggering the inverters

Avoiding the Miller cap by opposite going signals

 Repeater Design Issues
 Delay-optimal repeaters are area and power hungry – use of
sub-optimal insertion
 Optimal placement requires accurate modeling of
interconnect.
 Optimal placement not always possible.
 Performance limited due to significant interconnect
resistance.
 Source of noise – Supply and Substrate
 With Scaling …
60 6x106
50 5x106

rs

# of Repeaters
te
40 re 4x106
Wi

ea
Power(W)

ep
30 +
er s 3x106

#R
e a t
20 Rep 2x106
10 s On ly
W ir e 1x106
0 0.25 0.2 0.15 0.1 0.05
Technology Generation(m)
 1 million repeaters in a 100nm technology.
 Consuming about 30W (40%) in 100nm technology.
 Need to look at alternatives!!!
 Differential Transmission
 Limiting swing saves significant amount of power.
 Rejects common-mode noise.
 Coupling is reduced due to dipole cancellation O(n3)
 Doubled wire density --

300mv