Routing

The process of establishing physical

connections between different
components or nodes on a chip
Inputs of Routing
● Netlist
● CTS DEF file
● NDRs (Non-Default Rules)
● Physical library
● Timing library
● Tech file
Checks to proceed for routing
1) Timing: ( depends on project & tech node )
setup WNS <= 50ps

Hold WNS <= -20ps

2) NO MAX tran on CLK nets.

3) Check_legality should be clear.
4) NO congestion hotspots.
5) Clock net routing should be finished.

Note: Once all these are clear we can proceed to Routing.

Steps in routing
Cmd: route_auto (for automatic routing, It does only routing, It won’t
add any cells to the design)
1) Global Routing

Cmd: route_global.

2) Track assignment

Cmd: route_track

3) Detail Routing (MAX 40 Iterations)

Cmd: route_detail
Global Routing
● In global routing ,tool divides entire core area into GRC cells and tries to
find the path from pin to pin as per the logical connectivity to route
using the global cells
● During trail routing tool divides entire metal layer into number of GRC
cells.
● Each cells carries set of horizontal and vertical routing tracks.by using
those GRC cells tool do quick routing to estimate routing related
congestion and net parasitic values for optimization and timing analysis.
● While doing global routing tool tries to avoid routing over the routing
blockages and never touches the pre-routes.
● Tool do global routing by using Steiner Tree and Maze Algorithm
Global Routing
● Assign layers to the
nets.
● Avoid congested
areas and also long
detours.
Track Assignment
During the Track Assignment stage in physical design, the tool replaces
global routes with actual metal routes. These routes are not follow DRC
(Design Rule Check) requirements. Once real metals are used, potential
violations can occur, including:
● DRC violations
● Signal Integrity (SI) issues
● Timing violations
● The main tasks performed by the track assignment stage is
assigning real metal layers and rerouting the overlapping nets
Track Assignment
● Takes the Global Routed
Layout and assigns each
nets to the specific
Tracks and layer
geometry
● It does not follow the
physical DRC rules.
● It will do the timing
aware Track Assignment
● It helps in via
Minimization.
Detail Routing
● Detailed routing follows
up with the track
routed net segments
and performs the
complete DRC aware
and timing driven
routing.
● It is the final routing for
the design built after
the CTS and the timing
is freeze.
Detail Routing
● Detailed routing follows up with the track routed net segments and performs the
complete DRC aware and timing driven routing
● Based on DRC type, tool will either spread the wires or fill a gap. These fixes might
cause some more violations like notch filling can cause spacing violations because
of increased width and wire spreading can cause violation in adjacent region.
● Tool will analyze then and fix them. This is iterative loop.

Commands to check opens, shorts and DRC’s.

● Command to check shorts and opens: check_lvs
● Cmd to check detailed report of opens: check_lvs -open_reporting detailed.
● Command check_routes will update the new DRC’s.
● Open zroute.err in error browser to open drc errors.
● If 150 DRC,s are in single hotspot region, we should go back and check congestion
in that area.
● Fix the congestion and redo routing.
Route_opt
● To fix violations due to
1.Cross talk
2.RC correlation mismatch ( pre route vs post route)
3.Detours
● Route_opt command do’s optimization, legalization and incremental
routing. We can run it as many times we required.
● Command : Analyze_design -violations
● Analyze -design -stage post_route
● Collect all the reports (timing, utilization, DRC, Max tran, LVS).
Filler insertion
Post Route
● Gaps between Std cells need to be filled for N-well continuity.
● Filler cell is used to fill these gaps.
● It is a physical only cell with PG pins. Filler Insertion
● There are two types of filler cells
1. DCAP Fillers
2. Non-metal Fillers (Normal standard filler cells) PNR Outputs
● First DCAP Filler cells will be inserted
● DCAP Fillers causing M1 DRC’s will be removed by tool.
● Then Non-metal fillers cells will be inserted.
● Filler gaps are not allowed, will cause latch-up related base DRC
violations.
Command: create_stdcell_fillers -lib_cells [get_lib_cells *FILL*]
● Cmd for filler insertion : create_stdcell_fillers
● Order of filler cells should be from highest width to lowest width
● Ex: Fill 64, Fill32, Fill16, Fill8, Fill4, Fill2.

PNR OUTPUTS
● Netlist (write_verilog)

1. PG Netlist (VDD, VSS, Power & Signal info)

2. Non PG Netlist (Only signal info mainly used for Timing & LEC)
● DEF (Design Exchange Format) (write_def): Contains design specific
information like

Die size, Std cell location, Net routing information, PG routes.

● GDS- II (Graphic Design System) (write_gds)

Non-merged GDS (No Base layer information)

GDS-II
INNOVUS (or) ICC2

GDS (Doesn’t have any base layer

(FEOL) )

STD cell GDS → Provided by foundry

GDS Merging Macro GDS → Provided by macro vendors

Tools: PV Tools
Synopsys → IC Validator
FULL GDS Cadence → Peguses/PVS
Mentor Graphics → Calibre (Mostly Used)
Dummy Metal Fill
Purpose:
● To meet density rules mainly the min density rules.For every metal
layer, there is a rule for Min & Max density.

Tools used: PV Tools. PV TOOLS (SignOFF).

FULL GDS WITH FILL DRC, ERC, Anteens,
DUMMY METAL LVS
FULL GDS FILL
FILL ONLY GDS (ONLY Used For SPEF
(BEOL + LAYERS/SHAPES) Extraction
FEOL)
Tools used for GDS
RULE RULE PROVIDED BY
DECK DECK FOUNDRY View
● K2_Viewer
● Klayout
● Calibredrc
Shorts
When the shape (small segment of net) of two different nets
intersects/touches each other in the same layer, a short is reported.As
shown in below figure,the small portion of the red highlighted net is
touching the yellow highlighted net. Since both nets are different and in
the same metal layer, a short occurs

CMD: check_lvs (To check shorts & opens in the design)

CMD: check_routes
● Shift the red highlighted net to the left. Now, they don’t interfere
with each other, and the short is fixed .To verify and report shorted
nets by using any one of the above commands.

● If the design has shorts in single or double digits, they can be fixed
manually quickly and easily. However, if the design has shorts in
multiple thousands, the following approaches are preferred to get rid
of shorts.
● Delete shorted nets and reroute them by running eco route
while freezing the rest of the nets.
To remove shorted nets:
Remove_routes -detail_route -global_route -shield_route -nets
“<net_name>”
To route the removed nets:
route_eco -open_net_driven true.
● Run “route_detail”, which performs detail routing to help fix
shorts and DRCs. The following command performs detail
routing with a maximum iteration of 5. Try running multiple
loops of route_detail with increasing values of
max_number_iterations to minimize DRCs and shorts.
route_detail –max_number_iterations 5
DRC (Design Rule Checks)
● Design Rule Checking (DRC) verifies as to whether a specific design
meets the constraints imposed by the process technology to be
used for its manufacturing. DRC checking is an essential part of the
physical design flow and ensures the design meets manufacturing
requirements and will not result in a chip failure. The process
technology rules are provided by foundry
● All the rules, provided by the foundry, are fed as an input to the
Physical Verification Tool in the form of verification rule file (Rule
deck file for Physical Verification Tool). If any of the rules are
violated, the DRC will be reflected in the design.
Classification Of DRC
Types of DRC:

● Minimum width and spacing for metal

● Minimum width and spacing for via
● Fat wire Via keep out Enclosure
● End of Line spacing
● Minimum area
● Different net spacing
● Special notch spacing
● Shorts violation
● Different net Via cut spacing
● Less than min edge length
Base layer:

The DRCs – which are associated with FEOL (Front End of Line) Process include Nwell, N+, P+
implant layers, poly, Oxide Diffusion, etc. – are referred to as Base Layer DRC. The fixation of these
DRCs demands the alteration of FEOL layers

Some of the Causes for Base Violations are

1. Missing End Cap/WellTap/Decaps/Filler cells

2. Incorrect filler placement
3. Overlap of hard macros
4. Orientation issue
5. Input gate integrity problem
6. Legalization issue
7. Abutment requirement between two Memories is not met (Memory Spacing Rule varies in
accordance to technology and foundry)
Metal layers:
● The DRC associated with the BEOL (Back End of Line) Process are those
that include interconnects or metal layers which are plugged with FEOL
and external devices.
● Some Real Scenarios of Metal DRC Violations

1. CM1A.S.3.1

2. M4.A.1

3. VIA2.S.20
LINUX COMMANDS
● Path
1) Absolute path: An absolute path describes the complete location of a file or
directory from the root directory /.
2) Relative path: A relative path describes the location of a file or directory in
relation to the current working directory.
● pwd → Print working directory
● / → root directory.
● .. → one directory back.
● ~ → home directory.
● . → current directory.
● Cd → change directory
● To know more about the command we can use man and help.
1) man <any command>
2) <any command> --help
● ls → list objects.
● mkdir → create directory
● mkdir -p <path m1/m2/m3> → To create one directory in another directory.
● touch → To create a file.
● cat <path of the file> → To display information in file.
● cat > <path of a file> → To create information in files. [Ctrl+d to save]
● head -5 <path of the file> → To display specific lines in a file. Here it displays
first 5 lines.
● tail <path of the file > → To display last 10 lines, by default it displays 10
lines.
● cp <path of what we want to copy> <path that where we want to past> →
copy and paste.
● cp -r <path> <path> → To copy a directory.
● mv <path> <path> → To cut the files and past. It is also used to rename.
● rm <path of file what we want to delete> → To delete any file.
● rm -r <path of file or directory what we want to delete> → To delete
any directory.
● clear → To clear the terminal screen.
● history → To get the history of the commands what we are using.
● gzip → Compress a file.

Example: gzip -k file.txt .

● alias → Create command shortcuts.

Example: alias l=’ls-la’

● echo →Display a line of text
● tr →translate characters

Example:echo “indus” | tr ‘a-z’ ‘A-Z’

● $exit → To exit from any shell or tool
● Which → To know if that tool is there in our system or not
● expr → To do calculations on terminal
● find <path> <option> <value> <option 2> -type f/d -name
● Wild card characters : “*”, “?”.
● tree → Displays directories and files in a tree-like structure
● ps → Process status (Displays information about currently running processes)
● kill → Terminates a process by its process ID
● jobs →Lists background and suspended jobs in the current session
● bc → basic calculator
● wc → word count
● Cut → To get a particular character orelse a column from a file.
● Paste → Merges files line side by side
● Sleep → The terminal will be ideal for given time. (It can be seconds, minutes, hours
and days)
● Write → To communicate with other users on same server.
● date → It shows the date.
● whoami → user login details
● uname → Operating system using now.
● du -sh → directory space
● du -sh ~ →home directory space.
● df -kh → disk space
● meld r1.txt b1.txt & gvimdiff → To check the difference between two files
● echo $0 → To know current shell.
● Sort → To arrange content in alphabetical order.
● rename → It is used to change multiple file names at once.
● THERE ARE THREE MOST USEFUL AND POWERFUL COMMANDS IN LINUX
● grep → global regular expression print is used for text processing to select
things from multiple files by string match pattern match.
grep <option> “string match”
<file_path>
● sed → Stream Editor
● awk → Abstract window toolkit
Gvim Commands & Shortcuts
● gvim <file path> → To open existing file or to create a new file with given name.
● There are three modes in gvim. Command mode, Visual mode and Insert mode.
● Press “i” to enter into insert mode.
● Press “v” to enter into visual mode.
● Press “Ece” to enter into command mode.
● gvim -p <file path> <file path> → To open two or more files in one window.
➔ :qall → To close all files in one window.
➔ :u → undo, the last change.
➔ :5d → to delete 5th line.
➔ :q → To quit from gvim mode.
➔ :q! → closing file without saving (or) forcefully close.
➔ :w or w! → To save the changes in command mode.
➔ :!ls → To list.
➔ :set number (or) :se nu → To set numbers to lines.
➔ :6, :1 -> To move from one line to another line.
➔ :%s/search text/replace text/ → To replace first occurrence.
➔ :%s/search text/ replace text/g → To replace all occurrences.
➔ :sp → Horizontal split
➔ :vsp → vertical split
➔ :e → To close current file and open another file.
➔ O (or) o → To create a blank line and to insert.
➔ r → To replace one character or selecting a word.
➔ /<search text> → To search text. It highlights the text.
➔ ?<search text> It highlights the text.
➔ :nohl → to not highlight the text.
➔ n (or) N -> To move from one search to another or to the next
occurrence.
➔ Shift+8 or * → To highlight anything which is selected.
➔ h → To move the cursor to left.
➔ j → To move the cursor to down.
➔ k → To move the cursor to up.
➔ l → To move the cursor to right.
➔ $ → To move to last line.
➔ ^ → To move to first line.
➔ G → To move to last line of file.
➔ gg → To move to first line of file.
➔ Y → To copy the content, It should be done in visual mode.
➔ P → To paste the content, It should be done in command mode.
Commands Used in Routing
● check_design -checks -pre_route_stage
● Set_senario_status -active true [get_scenarios]
● report_app_options *si*enable*
● set_app_option -name time.si_enable_analysis -value true
● report_app_options *timing*driven*
● set_app_option -name route.detail.timing_driven -value true
● set_app_option -name route.global.timing_driven -value true
● report_app_options *cross*driven*
● set_app_option -name route.global.crosstalk_driven -value true
● set_app_option -name route.track.crosstalk_driven -value true
● route_global
● route_track
● route_detail
● check_lvs
● check_lvs -open_reporting detailed
● check_routes
● analyze_design_voilations
● Analyze_design_voilation -stage post_route
● create_stdcell_fillers
● connect_pg_net -automatic
● Remove_stdcell_fillers_with_violation
● connect_pg_net -automatic
● legalize_placement