Microprocessor Systems
Lecture Notes # 6
Dr. Mona Sayed
Outline of the Lecture
Flag Registers and bit fields
80x86 addressing modes
FLAG REGISTERS AND BIT FIELDS
Flag Register and ADD instruction
The flag bits affected by the ADD instructions are: CF, PF, AF, ZF, SF
and OF.
Ex: Show how the flag register is affected by the addition of 38H and
2FH.
CF = 0 since there is no carry beyond d7
PF = 0 since there is odd number of 1`s in the result
AF = 1 since there is a carry from d3 to d4
ZF = 0 since the result is not zero
SF = 0 since d7 of the result is zero
80X86 ADDRESSING MODES
The CPU can access operands (data) in various ways, called addressing
modes. In 80x86 there are 7 addressing modes
1. Register
2. Immediate
3. Direct
4. register indirect
5. based relative
6. indexed relative
7. based indexed relative
1. Register addressing mode:
involves the use of registers
memory is not accessed, so faster
source and destination registers must match in size.
2. Immediate addressing mode:
source operand is a constant
possible in all registers except segment and flag registers.
3. Direct addressing mode:
address of the data in memory comes immediately after the
instruction operand is a constant
The address is the offset address. The offset address is put in a
rectangular bracket.
4. Register indirect addressing mode:
The address of the memory location where the operand resides is held
by a register.
SI, DI and BX registers are used as the pointers to hold the offset
addresses.
They must be combined with DS to generate the 20-bit physical
address.
5. Based relative addressing mode:
BX and BP are known as the base registers. In this mode base
registers as well as a displacement value are used to calculate the effective address.
The default segments used for the calculation of Physical address
(PA) are DS for BX, and SS for BP.
Note that, the content of the low address will go into CL and the high address
contents will go into CH.
There are alternative coding: MOV CX,[BX+10], MOV CX,10[BX]
BX+10 is effective address
6. Indexed relative addressing mode:
Indexed relative addressing mode works the same as the based
relative addressing mode.
Except the registers DI and SI holds the offset address.
7. Based Indexed addressing mode:
The combination of the based and indexed addressing modes.
One base register and one index register are used.
Offset Registers for various Segments
