Chapter Two

Intel 8086/8088- Hardware

Specification

1
Outline
 Internal Architecture of 8086/8088

 Features of 8086 Microprocessor

 EU & BIU

 General Purpose Registers, Index & Pointer registers,

Flag Registers, Segment Registers, Instruction Queue.

2
 Introduction
 The microprocessor is composed of:
• A register section
• One or more ALUs
• A control unit

 Depending on the register section, the microprocessor

can be classified:
• accumulator-based
• general purpose register based

3
 Intro

• Accumulator-based:
• one of the operands is assumed to be held in a special
register called “accumulator”
• All AL operations are performed using this register

• Result of operation is also stored here

• 8-bit MPs are usually accumulator-based

• e.g. Intel 8085 and Motorola 6809

4
 Cont. . .
• The general-purpose register-based:
– usually popular with 16 and 32-bit MPs
– e.g. Intel 8086/80386, MC 68000/68020 are called general
purpose microprocessors since registers are used to hold data,
memory address or results of operation
– Some of the registers are general purpose, others have dedicated
functions
– A GP register is also capable of manipulating stored data by
shift operations

5
 Cont. …
• These registers are normally 8, 16 or 32 bits wide
• E.g. all general purpose registers of 68000 are 32 bits and can be
used as either 8, 16 or 32 bits
• Typical dedicated registers include:
– Program Counter (PC)
– Instruction Register (IR)
– Status Register (SR)
– Stack pointer Register (SP)
– Interrupt Resister (IntR)

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 Cont. …
• The ALU
– performs all arithmetic and logic operations on data
– Size of ALU defines size of MP
– Eg Intel 8086 is 16-bit, since its ALU is 16 bits wide.
68030 is 32-bit
• The control unit (CU)
– performs instruction interpretation and sequencing
– interpretation phase:
• CPU reads instructions from memory using PC as a pointer
• recognizes the instruction type
• gets the necessary operands
• Sends them to execution unit (EU)
• Issues signals to EU to perform operations
7
 Cont. ..
• sequencing phase:

– determines the address of the next instruction to be executed

– loads it into the PC

• is typically designed using one of three techniques:

– Hardwired control – by physically connecting typical components

such as gates and ffs
– Microprogramming – using control ROM for translating instructions
(e.g. intel 8086 is mciroprogrammed mp)
– Nanoprogramming – includes two ROMs inside the control unit. The
first (microROM)stores all the addresses of the second
ROM(nanoROM) e.g. 68000, 020, 030 8
The Intel 8086 was Intel’s first x86 processor. Intel’s 8086/8088
µ-p is packaged in a 40-pin Dual in-line Packages (DIP) and it
requires a +5.0 V power supply.

9
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology (HCMOS)
32 bit processors
Third Generation Physical memory space 224 bytes = 16 Mb
During 1978 Virtual memory space 240 bytes = 1 Tb
HMOS technology  Faster speed, Higher packing Floating point hardware
density Supports increased number of addressing modes
16 bit processors  40/ 48/ 64 pins
Easier to program Intel 80386
Dynamically relatable programs
Processor has multiply/ divide arithmetic hardware
More powerful interrupt handling capabilities
Flexible I/O port addressing
Second Generation
Intel 8086 (16 bit processor) During 1973
NMOS technology  Faster speed, Higher density,
Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces and I/O
Between 1971 – 1973 ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine nesting
4 bit processors  16 pins Better interrupt handling capabilities
8 and 16 bit processors  40 pins
Intel 8085 (8 bit processor)
Due to limitations of pins, signals are multiplexed
10
 Microprocessor Functional blocks
Computational Unit; Various conditions of the
performs arithmetic and logic results are stored as status Internal storage of data
operations bits called flags in flag register

Register array or Data Bus

internal memory
ALU
Generates the
Instruction address of the
Flag decoding unit instructions to be
Register fetched from the
memory and send
through address bus
Timing and
PC/ IP to the memory
control unit

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations of information to the timing and
the microprocessor control unit 11
8086 Microprocessor

Overview
 First 16- bit processor released by INTEL
in the year 1978
 Originally HMOS, now manufactured
using HMOS III technique
 Approximately 29, 000 transistors, 40 pin
DIP, 5V supply
 Does not have internal clock; external
asymmetric clock source with 33% duty
cycle
 20-bit address to access memory  can
address up to 220 = 1 megabytes of memory
space.

12
 The 8086/8088 pin architectures use the combined address and
data bus format commonly referred as a time multiplexed
address and data bus.
 One advantage behind the multiplexed address/data bus is the
maximum utilisation of processor pins (since the same pins
carry address/data) and it facilitates the use of 40 pin standard
DIP package.
 The bus can be de-multiplexed using a few latches and trans
receivers, whenever required.

13
 8086 has a 20 bit address bus and can access up to 1 MB
1,048,576 (220) memory locations.
 8086 has a 16bit data bus, so it can read or write data to a
memory/port either 16bits or 8 bit at a time.
 It provides 14/16 -bit registers.

 It can pre-fetch up to 6 instruction bytes from memory and queues

them in order to speed up instruction execution.
 It has 256 vectored interrupts.

 It consists of 29,000 transistors.

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 8088 has a 20 bit address bus and can access up to 1 MB (2 20)
memory locations.
 8088 has a 8-bit external data bus, so it can read or write 8 bit data to
a memory/port at a time.
 It provides 14/16 -bit registers.
 It can pre-fetch up to 4 instruction bytes from memory and queues
them in order to speed up instruction execution.
 Clock speed- 8086 has 3 available clock speeds (5 MHz, 8 MHz
(8086-2) and 10 MHz (8086-1)) where as 8088 has 2 available
clock speeds (5 MHz, 8 MHz)
 Signal- 8086 has Bank High Enable (BHE) signal. 8088 has
Status Signal (SSO).
 8086 has memory control pin (M/IO) signal whereas 8088 has
complemented memory control pin (IO/M) signal of 8086.

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• Comparison between 8085 & 8086
 Microprocessor Size − 8085 is 8-bit microprocessor, whereas
8086 is 16-bit microprocessor.
 Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit
address bus.
 Memory − 8085 can access up to 64Kb, whereas 8086 can access
up to 1 Mb of memory.
 Instruction − 8085 doesn’t have an instruction queue, whereas
8086 has an instruction queue.
 Pipelining − 8085 doesn’t support a pipelined architecture while
8086 supports a pipelined architecture.

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• Cont…
 I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can
access 2^16 = 65,536 I/O’s.
 Cost − The cost of 8085 is low whereas that of 8086 is high.

17
Pin-outs and its functions

18
The Pin-configuration of 8086 µP IC:

19
20
 The 8086/8088 operates in single processor or multiprocessor
configuration to achieve high performance.
 8086/8088 is designed to operate in two modes, Minimum mode
and Maximum mode.
 The pins serve a particular function in minimum mode (single
processor mode) and other function in maximum mode
configuration (multiprocessor mode ).

21
The minimum mode is selected by connecting MN / MX pin
directly to +5.0 V (applying logic 1 to the MN / MX input pin).
This is a single microprocessor configuration
–The maximum mode is selected by applying logic 0 to the MN /
MX input pin. This is a multi micro processor configuration

22
 Minimum mode
 There is a single microprocessor in the minimum mode system.
 Latches are used for separating the valid address from the
multiplexed address/data signals and are controlled by the ALE
signal.

Maximum mode
• In the maximum mode, there may be more than one processor in
the system configuration.
• In this mode, the processor derives the status signal S2, S1, S0.

23
 Trans receivers are the bidirectional buffers and some
times they are called as data amplifiers.
 Trans receivers separate the valid data from the
multiplexed address/data signals.
 They are controlled by two signals namely, DEN and
DT/R.

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Description….

25
26
27
 Status bit S6 is always remains a logic 0, status bit S5
indicates the condition of the IF flag bits, and S4 & S3
show which segment is accessed during the current bus
cycle.
S4 S3 Function

0 0 Extra segment

0 1 Stack segment

1 0 Code segment or no segment

1 1 Data segment

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29
30
31
32
33
34
35
36
S2 S1 S0 Indication

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

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38
 Queue Status Bits

QS1 QS0 Indication

No Operation
0 0
First Byte of the opcode from
0 1 the queue
1 0 Empty Queue

1 1 Subsequent Byte of opcode

from the Queue

39
Internal Architecture
8086 µP

40
8086 Internal Architecture

41
 Internal Architecture of 8086 µ-p is internally
divided into two separate functional units.

Bus Interface Unit (BIU)

Execution Unit (EU)

42
• Both units operate synchronously to give the 8086, an
overlapping of instruction fetch and execution
mechanism.
• By pre-fetching the instruction, there is a considerable
speeding up in instruction execution in 8086. This is
known as instruction pipelining.
• This results efficient use of the system bus and system
performance.

43
• BIU contains - Instruction queue, Segment
registers, Instruction pointer, Address adder.

• EU contains - Control circuitry, Instruction

decoder, ALU, Pointer and Index register, Flag
register.

44
• BIU
– Fetches instructions.
– Read data from memory and I/O ports.
– Write data to memory and I/O ports.
– Interfaces the 8086 µp to the outside world.
– Instruction queuing, Operand fetch & storage and
Bus control.
• EU
– Executes instructions that have already been fetched
by BIU.

45
 Bus Interface Unit (BIU)
The BIU’s instruction queue is a FIFO (First In First Out)
group of registers in which up to 6 bytes of instruction code can
be pre-fetched from memory ahead of time. This is done in order
to speed up the program execution by overlapping instruction
fetch with execution, termed as instruction pipelining.
The BIU contains a dedicated adder which is used to produce
20-bit address.
The bus control logic unit of the BIU generates all the bus
control signals such as read and write signals for memory and
I/O.

46
• If the BIU is already in the process of fetching an
instruction when the EU request it to read or write
operands from memory or I/O, the BIU will first
completes the instruction fetch bus cycle before
initiating the operand read/write cycle.

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 Execution Unit
The Execution unit is responsible for decoding
and executing all instructions.
During the execution of the instruction, the
EU tests the status and control flags and
updates them based on the results of the
executing instruction.
If the queue is empty, the EU waits for the
next instruction byte to be fetched and shifted
to top of the queue
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When the EU executes a branch or jump instruction, it transfers
control to a location corresponding to another set of sequential
instructions.
Whenever this happens, the BIU automatically resets the queue
and then begins to fetch instructions from this new location to refill
the queue.
The EU has 16 bit ALU for performing arithmetic and logic
instructions.

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 FLAG Register in the EU

 8086 has a 16 bit 3 control and 6 status flag register.

The FLAG register in the EU holds the status flags

typically after an ALU operation.

50
 Register set of 8086
• The 8086 microprocessor has a total of fourteen
registers that are accessible to the programmer. It is
divided into four groups.
• They are:
– Four (16-bit) General purpose registers
– Four (16-bit) Index/Pointer registers
– Four Segment registers
– Two Other registers

51
General Purpose
registers

52
• These data registers are general purpose registers, but
they perform some special functions too.

53
Accumulator (AX) register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. In this case, AL contains the low
order byte of the word, and AH contains the high-order byte.
The input /output instructions always use AX or AL for inputting/outputting 16/8 bit
data to or from an I/O port.
 Preferred register to use in arithmetic, logic and data transfer instructions because
it generates the shortest Machine Language Code
 Must be used in multiplication and division operation
 Must also be used in I/O operations

54
Base register (BX) consists of two 8-bit registers BL and BH,
which can be combined together and used as a 16-bit register
BX. In this case, BL contains the low-order byte of the word,
and BH contains the high-order byte.
The contents of this register can be used for
addressing 8086 memory. It sometimes holds the
offset address of a location in the memory system.
BX register usually contains a data pointer used for
based, based indexed or register indirect addressing .
Also serves as an address register.

55
• Count register (CX) consists of two 8-bit registers CL and CH,
which can be combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of the
word, and CH contains the high-order byte.
– Count register normally used as a Loop counter.
– It holds the count for various instructions like REP
(repeated string instructions),Shift, rotate, loop etc.
Normally the shift and rotate instructions use CL as
the counts and the repeated string instructions and
looping instructions use CX as the count.

56
Data register (DX) consists of two 8-bit registers DL
and DH, which can be combined together and used as
a 16-bit register DX. When combined, DL register
contains the low order byte of the word, and DH
contains the high-order byte.
Data register can be used as a port number in I/O
operations.
The data register (DX) holds a part of the result
from a multiplication or part of the dividend before
a division and a remainder after the division.
Also used in I/O operations.

57
 Index and Pointer Registers
These registers can also be called as Special Purpose
registers.
Contain the offset addresses of memory locations
Can be used in arithmetic and other operations as well.

58
Stack Pointer (SP) is a 16-bit register pointing the stack. i.e, it is
used to hold the address of the top of stack. The stack is
maintained as a LIFO (specified by the SS segment register).
The SP contents are automatically updated (incremented
/decremented) due to execution of POP or PUSH instruction
Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. ( BP register is usually used for based, based indexed or
register indirect addressing).
 primarily used to access data on the stack and in other
segments
Unlike the SP register, the BP can be used to specify the offset of
other program segments.
It is also used for memory data transfers.

59
Source Index (SI) is a 16-bit register. SI is used (for indexed,
based indexed and register indirect addressing), as a source data
address in string manipulation instructions.
 is required for string operations
 when string operations are performed, the SI register points to
the memory locations in the data segment which is addressed
by DS register.
 Used in conjunction with the DS register to point to data
locations in the data segment.
 thus, SI is associated with the DS in string operations.

60
Destination Index (DI) is a 16-bit register. DI is used (for indexed,
based indexed and register indirect addressing) as a destination
data address in string manipulation instructions.
 when string operations are performed, the DI register points to
the memory locations which is addressed by ES register.
 thus, DI is associated with the ES register in string operations.
In short, DI and SI registers are normally used to hold offset
addresses.
The SI and DI registers may also be used to access data stored in
arrays.

61
 Segment Registers
• There are four different segments (64KB each) for
instructions/code, data, stack and extra data.
• To specify where these 4 segments are located in 1 MB of
processor memory, the 8086 microprocessor uses 4 segment
registers: They are
– CS Code Segment
– DS Data Segment
– SS Stack Segment
– ES Extra Segment
• Segment registers are address registers which store
the starting addresses of memory segments.

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Code Segment (CS) is a 16-bit register containing the starting
address of 64 KB segment with processor instructions/code.
The processor uses code segment for all accesses to instructions
referenced by instruction pointer (IP) register.
CS register cannot be changed directly.
The 16 bit contents of Instruction Pointer (IP) is used as an offset for
computing the 20 bit physical address
Stack Segment (SS) is a 16-bit register containing the starting
address of 64KB segment with program stack.
 By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack
segment.
 SS register can be changed directly using POP instruction.

63
Data Segment (DS) is a 16-bit register containing the starting
address of 64KB segment with program data.
 By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment.
 DS register can be changed directly using LDS instructions.
 SI and DI are used as an offset for computing the 20 bit
physical address.
Extra Segment (ES) is a 16-bit register containing the starting
address of 64KB segment, usually with program data.
 By default, the processor assumes that the DI register references the
ES, especially in string manipulation instructions.
 ES register can be changed directly using LES instructions.
 String instructions always use ES and DI to determine the 20
bit physical address for the destination.

64
• A combination of a Segment Address and an Offset Address
access a memory location in the real mode.
• The Segment Address [located within one of the segment
registers] is the beginning address of any 64KB memory
segment.
• The Offset Address selects any location within the 64KB
memory segment.

65
In the real mode, each segment register is internally appended
with a 0H (or 016) on its right most end to form a 20-bit
memory address.
The µ-p must generate a 20-bit memory address to access a
location within the first 1MB of memory.
For instance when a CS register (a register in the segment
register) contains a 1200H; it addresses a 64KB memory
segment beginning at location 12000H.

66
• All program instructions located in main memory is pointed by
the 16-bit CS Register along with a 16-bit Instruction Pointer (IP)
as an offset.
• IP (Instruction pointer) addresses or points the next instruction in
a program.
 The µ-p has a set of rules that apply to segments whenever
memory is addressed. These rules, which apply in real mode,
define the segment register and offset register combination.
 For e.g. a code segment (CS) register is always with the
instruction pointer (IP) to address the next instruction in a
program. The code segment (CS) register defines the start of the
code segment and IP locates the next instruction executed by the
µ-p.

67
Memory Segmentation in 8086
Microprocessor

68
• Segmentation is the process in which the main memory of the
computer is logically divided into different segments and each
segment has its own base address.
• It is basically used to enhance the speed of execution of the
computer system, so that the processor is able to fetch and execute
the data from the memory easily and fast
• 8086 can effectively address only 64 KB of memory, since the
memory is divided into 64 KB sized segments.
• Program/code, data and stack memories occupy different spaces in
the same 1MB sized memory.
• To access the memory, the CPU uses special registers called as
segment registers to specify where the code, data and stack are
positioned within 1MB of memory.

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• Memory address (20-bit) in 8086 are expressed as a 5 hexa
decimal digits from 00000H- FFFFFH
• But 20-bit addresses are too big to fit in 16-bit registers!
• The solution is memory segmentation
 The memory in 8086 based system is organized as segmented
memory.
 In this scheme, the logical segments (each of 64KB in size) are
addressed by one of the segment registers.
 The 16 bit segment register will hold the starting
location/address(segment address) of a particular segment.

70
A segment address is a 16-bit address.
The CPU must generate 20-bit memory address to access a
location within the first 1MB of memory.
Within a memory segment, a particular memory location is
specified with an offset.
An offset is the difference from the beginning of a segment to a
particular memory location.
An offset also ranges from 0000F- FFFFH (16-bit)
To address a specific memory location within a segment, we need
an offset address also.

71
Memory segmentation example

FFFFFH

7FFFFH TOP OF EXTRA SEGMENT

64K ES

70000H EXTRA SEGMENT BASE

ES = 7000H
5FFFFH TOP OF STACK SEGMENT

64K SS

50000H STACK SEGMENT BASE

SS = 5000H
4489FH TOP OF CODE SEGMENT

64K CS

348A0H CODE SEGMENT BASE

CS = 348AH
2FFFFH TOP OF DATA SEGMENT

64K DS

20000H BOTTOM OF DATA SEGMENT

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Generation of 20-bit physical
address

73
 Generating physical address of code
byte:

PHYSICAL MEMORY
ADDRESS
TOP OF CODE SEGMENT
2FFFFH

38AB4H CODE BYTE

IP=4214H

348A0H START OF CODE SEGMENT

CS = 348AH

CS 3 4 8 A 0 HARD WIRED ZERO

IP + 3 4 8 A
PHYSICAL ADDRESS 3 7 D 2 A
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 Example:
• Generate 20-bit physical address for the following:
start of code seg CS = 2F84
offset IP = 0532
=>

CS 2 F 8 4 0
IP + 0 5 3 2
2 F D 7 2

• Alternative way of representing 20-bit physical

address:
segment base : offset
i.e CS : IP
e.g. 348A : 4214
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1. If a physical branch address is 5A230 H when
(CS) = 5200 H, what will it be if the (CS) are changed to
7800 H.
CS: 52 0 0
Offset: XXXX
Physical add. 5A2 3 0 H
Hence Offset = Physical add - (Segment address displaced by 4-bits)
Offset = 5A230 - 52000 = 8230 H
If the CS is changed to 7800 H the Physical address will be
78000 + 8230 = 80230
2. Given that the EA of a datum is 2359 H and the DS = 490B H, what is the
physical address of the datum?
DS: 490B0 H
EA: 2359 H
Physical add. 4B409
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 Default Segment and Offset Registers

Segment Offset Special Purpose

CS IP Instruction address

SS SP or BP Stack address

DS BX,DI,SI Data address

ES DI String destination address

77
Other registers of 8086

78
Instruction Pointer (IP).
This is a crucially important 16-bit register, which is used to
control which instruction the CPU executes.
The IP, or program counter, is used to store the memory
location of the next instruction to be executed.
The CPU checks the IP to ascertain which instruction to carry
out next. It then updates the IP to point to the next instruction.

79
Flag Register contains a group of status bits called flags
that indicate the status of the CPU or the result of an
arithmetic operation. There are two types of flags:
 The status flags which reflect the result of an executing
instruction. The programmer cannot set/reset these flags
directly.
 The control flags enable or disable certain CPU operations.
The programmer can set/reset these bits to control the CPU's
operations.

80
• Nine individual bits (out of 16) of the status
register are used. 3 of them are control flags
and 6 of them are status flags. The remaining 7
are not used.
• A flag can only take on the values 0 and 1.
• The status flags are used to record specific
characteristics of arithmetic and of logical
instructions.

81
82
 3 Control Flags
The Direction Flag (D): Affects the direction of moving data blocks
by the string instructions like MOVS, CMPS etc...
The flag values can be set/reset by the STD (set D) and CLD (clear D)
instructions. Setting DF=1 causes the string instructions to auto
decrement and setting DF=0 causes the string instructions to auto
increment.
The Interrupt Flag (I): Dictates whether or not a system interrupts can
occur. Interrupts are actions initiated by hardware block such as input
devices that will interrupt the normal execution of programs.
The flag values are 0 = disable interrupts, or 1 = enable interrupts and
can be manipulated by the CLI (clear I) and STI (set I) instructions.
The Trap Flag (T): Determines whether the CPU has halted or not
after the execution of an instruction. This will be done for each
execution .
When this flag is set (i.e. = 1), the programmer can step through his
program to debug for once. When this flag = 0 this feature is disabled.
This flag can be set by the INT 3 instruction. 83
 6 Status Flags
The Carry Flag (C): set when the result of an unsigned arithmetic
operation is too large to fit in the destination register. This happens
when there is an end carry in an addition operation or there an end
borrow in a subtraction operation. A value of 1 = carry and 0 = no
carry.
The Overflow Flag (O): This flag is set when the result of a signed
arithmetic operation is too large to fit in the destination register (i.e.
when an overflow occurs). Overflow can occur when adding two
numbers with the same sign (i.e. both positive or both negative). A
value of 1 = overflow and 0 = no overflow.
The Sign Flag (S): This flag is set when the result of an arithmetic or
logic operation is negative. A value of 1 means negative, and 0 means
positive.

84
 6 Status Flags
The Zero Flag (Z): This flag is set when the result of an
arithmetic or logic operation is equal to zero. A value of 1
means the result is zero and a value of 0 means the result is
not zero.
The Auxiliary Carry Flag (A): This flag is set when an
operation causes a carry from bit 3 to bit 4 (or a borrow
from bit 4 to bit 3) for a BCD operation. A value of 1 = carry
and 0 = no carry.
The Parity Flag (P): This flags reflects the number of 1s in
the result of an operation. If the number of 1s is even its
value = 1 and if the number of 1s is odd then its value = 0.

85
 (Auxiliary Carry Flag) is used by BCD arithmetic instructions.
AF AF=1 if there is a carry from the low nibble into high nibble or a
borrow from the high nibble into low nibble.
(Carry Flag) is set if there is a carry from addition or borrow from
CF
subtraction.
OF (Over Flow Flag) is set, if there is an arithmetic overflow, ie when the
size of the result exceeds the capacity of the destination location.

SF (Sign Flag) is set if the MSB of the result is 1(-ve) and is cleared to 0 for
a non negative result.
(Parity Flag) is set if the result has even parity; and PF=0 for odd parity
PF of the result.
(Parity is a count of 1’s in a binary number expressed as even or odd. for
eg; if a number contains, 3 binary 1 bits, it has odd parity.)

ZF (Zero Flag) is set if result of an arithmetic and logic operation is zero. If

z=1, the result is zero and if z=0, the result is not a zero.

86
 (Direction Flag) setting DF=1 causes string instructions to auto
D decrement and clearing DF=0 causes string instructions to auto
increment. The D flag is set with STD(set direction) and D flag is
cleared with CLD(clear direction).

(Interrupt Flag) setting IF=1 causes 8086 to enable INTR(Interrupt

I Request) pin. Setting IF=0 causes INTR pin in a disabled state.
STI(Set I Flag) is used to enable INTR pin.
CLI(Clear I Flag) is used to disable INTR pin.

(Trace Flag) If T flag is enabled (=1), the µ-p interrupts

the flow of the program on conditions (as indicated by
T
debug registers and control registers). If T flag=0 the
tracing or trapping (debugging) feature is disabled.

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Flag Meaning SET RESET Flag Meaning SET RESET

CF Carry CY NC SF Sign NG PL

PF Parity PE PO IF Interrupt EI DI

AF Auxiliary AC NA DF Direction DN UP

ZF Zero ZR NZ OF Overflow OV NV

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Thank you.

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