Amrita School Of Engineering, Bangalore Campus
INSTRUCTION SET
LECTURE - 4
PREVIOUSLY
➤ Data Processing Instructions
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TODAY…
➤ Data Processing Instructions – Contd…
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CPSR FLAGS
➤ Carry/~Borrow
➤ In unsigned arithmetic, watch the carry flag to detect
errors.
➤ Bit goes from MSB
➤ Overflow
➤ In signed arithmetic, watch the overflow flag to detect
errors.
➤ Will be set if an overflow occurs into bit 31 of the result
➤ Negative
➤ Set to the logical value of bit 31 of the result
➤ Zero
➤ Sets only if result is zero
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CONTD…
➤ Logical Instructions
➤ V Flag unaffected
➤ C flag will be set to the carry out from the barrel
shifter
➤ Z flag will be set if and only if the result is all
zeros
➤ N flag will be set to the logical value of bit 31 of
the result.
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CONTD…
➤ Arithmetic Instructions
➤ V/C flag based on Signed/Unsigned
➤ Z flag will be set if and only if the result was zero
➤ N flag will be set to the value of bit 31 of the
result
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FLAGS FOR MUL INSTRUCTIONS
➤ The N (Negative) and Z (Zero) flags are set correctly
on the result
➤ N is made equal to bit 31 of the result
➤ Z is set if and only if the result is zero.
➤ The C (Carry) flag is set to a meaningless value
➤ V (oVerflow) flag is unaffected.
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INSTRUCTION FORMAT
➤ Ex: ADD r5,r1,r2;
➤ Rd destination reg
➤ Rn first source operand
➤ Operand2 second source operand
➤ I If 0, second source is a register else second source is 12-bit
imm.
➤ S set cond code
➤ F Instrn format, 0 = data processing instrn format
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CONTD…
➤ What ARM instruction does this represent?
➤ Hint: Opcode 4 is ADD
ADD R1, R0, R2
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LOGICAL OPERATIONS
➤ AND ; &
➤ ORR ; |
➤ MVN ; ~ MOV
➤ LSL ; <<
➤ LSR ; >>
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CONTD…
➤ Shift the second operand:
➤ ADD r5, r1, r2, LSL #2;
➤ r5 = r1 + (r2<<2)
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CONTD…
➤ Shift right r5 by 4-bits and place the result in r6?
MOV r6,r5, LSR #4;
MOV r6,r5, LSR r3;
➤ r6 = r5 >> r3
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CONTD…
➤ Instruction format??
➤ 12-bits operand2 field is interpreted as:
Shift = Type of shift
4th bit = 0 Shift_amt = Imme
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4th bit = 1 Shift_amt = Rs 13
SUMMARY
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LOAD / STORE INSTRUCTIONS
➤ The ARM is a Load / Store Architecture:
➤ Does not support memory to memory data processing operations.
➤ Must move data values into registers before using them.
➤ This might sound inefficient, but in practice isn’t:
➤ Load data values from memory into registers.
➤ Process data in registers using a number of data processing instructions which
are not slowed down by memory access.
➤ Store results from registers out to memory.
➤ The ARM has three sets of instructions which interact with
main memory. These are:
➤ Single register data transfer (LDR / STR).
➤ Block data transfer (LDM/STM).
➤ Single Data Swap (SWP).
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SINGLE REGISTER DATA TRANSFER
➤ The basic load and store instructions are:
➤ Load and Store Word or Byte
➤ LDR / STR / LDRB / STRB
➤ ARM Architecture Version 4 also adds support for halfwords and signed
data.
➤ Load and Store Halfword
➤ LDRH / STRH
➤ Load Signed Byte or Halfword - load value and sign extend it to 32 bits.
➤ LDRSB / LDRSH
➤ STRSB/STRSH is not available.
➤ All of these instructions can be conditionally executed by inserting the
appropriate condition code after STR / LDR.
➤ e.g. LDREQB
➤ Syntax:
➤ <LDR|STR>{<cond>}{<size>} Rd, <address>
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LOAD AND STORE WORD OR BYTE:
BASE REGISTER
➤ The memory location to be accessed is held in a
base register
➤ STR r0, [r1] ; Store contents of r0 to location pointed to by
contents of r1.
➤ LDR r2, [r1] ; Load r2 with contents of memory location
pointed to by contents of r1.
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LOAD AND STORE WORD OR
BYTE:OFFSETS
➤
FROM THE BASE REGISTER
As well as accessing the actual location contained in the base register, these
instructions can access a location offset from the base register pointer.
➤ This offset can be
➤ An unsigned 12bit immediate value (i.e. 0 - 4095 bytes).
➤ A register, optionally shifted by an immediate value
➤ This can be either added or subtracted from the base register:
➤ Prefix the offset value or register with ‘+’ (default) or ‘-’.
➤ This offset can be applied:
➤ before the transfer is made: Pre-indexed addressing
➤ optionally auto-incrementing the base register, by postfixing the instruction with
an ‘!’.
➤ after the transfer is made: Post-indexed addressing
➤ causing the base register to be auto-incremented.
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LOAD AND STORE WORD OR
BYTE:PRE-INDEXED ADDRESSING
➤ To store to location 0x1f4 instead use: STR r0, [r1,#-12]
➤ To auto-increment base pointer to 0x20c use: STR r0, [r1, #12]!
➤ If r2 contains 3, access 0x20c by multiplying this by 4:
➤ STR r0, [r1, r2, LSL #2]
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LOAD AND STORE WORD OR
BYTE:POST-INDEXED
➤ ADDRESSING
➤ To auto-increment the base register to location 0x1f4 instead
use:
➤ STR r0, [r1], #-12
➤ If r2 contains 3, auto-increment base register to 0x20c by
multiplying this by 4:
➤ STR r0, [r1], r2, LSL #2
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INSTRUCTION ENCODING
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USE OF PC
➤ Write-back must not be specified if R15 is specified as
the base register (Rn).
➤ R15 must not be specified as the register offset (Rm).
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EXAMPLE USAGE OF ADDRESSING
MODES
➤Imagine an array, the first element of which is pointed to by the
contents of r0.
➤ If we want to access a particular element, then we can use pre-
indexed addressing:
➤ r1 is element we want.
➤ LDR r2, [r0, r1, LSL #2]
➤ If we want to step through every element of the array, for instance to
produce sum of elements in the array, then we can use post-indexed
addressing within a loop:
➤ r1 is address of current element (initially equal to r0).
➤ LDR r2, [r1], #4
➤ Use a further register to store the address of final element, so that the
loop can be correctly terminated.
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OFFSETS FOR HALFWORD AND SIGNED
HALFWORD / BYTE
➤ The Load and Store ACCESS
Halfword and Load Signed Byte or
Halfword instructions can make use of pre- and post-
indexed addressing in much the same way as the basic
load and store instructions.
➤ However the actual offset formats are more
constrained:
➤ The immediate value is limited to 8 bits (rather than 12 bits)
giving an offset of 0-255 bytes.
➤ The register form cannot have a shift applied to it.
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INSTRUCTION ENCODING – WITH
REGISTER OFFSET
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INSTRUCTION ENCODING – WITH
IMMEDIATE OFFSET
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Quick Recap
➤ Register-indirect addressing
➤ LDR r0, [r1] ; r0 := mem32 [r1] ;
➤ STR r0, [r1] ; mem32[r1] := r0
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Quick Recap
➤ Base plus offset addressing
➤ LDR r0, [r1, #4] ; r0 := mem32 [r1+4] ;
This is a pre-indexed addressing mode.
➤ LDR r0, [r1, #4]! ; r0 := mem32 [r1+4] ;
r1 := r1 + 4
This is a pre-indexed addressing mode with auto-
indexing.
The exclamation mark indicates that the instruction
should update the base register after initiating the
data transfer.
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Quick Recap
➤ Base plus offset addressing
➤ Post-indexed addressing:
➤ LDR r0, [r1], #4 ; r0 := mem32 [r1] ;
r1 := r1 + 4
Here the exclamation mark is not needed, since the
only use of the immediate offset is as a base
register modifier.
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Multiple register data transfer
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Stack Addressing
➤ FA (Full Ascending) , FD (Full Descending)
➤ EA (Empty Ascending), ED (Empty Descending)
➤ A stack is usually implemented as a linear data
structure which grows up (an ascending stack) or
down (a descending stack) memory as data is added
to it and shrinks back as data is removed.
➤ stack pointer holds the address of the current top of
the stack, either by pointing to the last valid data item
pushed onto the stack (a full stack), or by pointing to
the vacant slot where the next data item will be placed
(an empty stack).
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STACK EXAMPLES
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CONTD…
➤ The stack type to be used is given by the postfix to the
instruction:
➤ STMFD / LDMFD : Full Descending stack
➤ STMFA / LDMFA : Full Ascending stack.
➤ STMED / LDMED : Empty Descending stack
➤ STMEA / LDMEA : Empty Ascending stack
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BLOCK COPY ADDRESSING
➤ Although the stack view of multiple register transfer
instructions is useful, there are occasions when a
different view is easier to understand. For example,
when these instructions are used to copy a block of
data from one place in memory to another a
mechanistic view of the addressing process is more
useful.
➤ Therefore the ARM assembler supports two different
views of the addressing mechanism, both of which
map onto the same basic instructions, and which can
be used interchangeably.
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BLOCK COPY ADDRESSING
➤ The block copy view is based on whether the data is to
be stored above or below the address held in the base
register and whether the address incrementing or
decrementing begins before or after storing the first
value.
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BLOCK COPY ADDRESSING
➤ The base register value before the instruction is r9, and after the auto-indexing it is r9'.
Multiple register transfer addressing modes.
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DIRECT FUNCTIONALITY OF
BLOCK DATA TRANSFER
➤ When LDM / STM are not being used to implement
stacks, it is clearer to specify exactly what
functionality of the instruction is:
➤ i.e. specify whether to increment / decrement the base
pointer, before or after the memory access.
➤ In order to do this, LDM / STM support a further syntax
in addition to the stack one:
➤ STMIA / LDMIA : Increment After
➤ STMIB / LDMIB : Increment Before
➤ STMDA / LDMDA : Decrement After
➤ STMDB / LDMDB : Decrement Before
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Stack vs Block copy view:
The mapping between the stack and block copy views of the load and store
multiple instructions.
13th May 2020
CONTD… (we will try this in lab)
➤ Copy a block of memory, which is an exact multiple of 12 words long
from the location pointed to by r12 to the location pointed to by r13.
r14 points to the end of block to be copied.
→ r12 points to the start of the source data
→r14 points to the end of the source data
→r13 points to the start of the destination data
loop LDMIA r12!, {r0-r11} ; load 48 bytes
STMIA r13!, {r0-r11} ; and store them
CMP r12, r14 ; check for the end
BNE loop ; and loop until done
Do we really require loop?
Isn’t the following two lines enough?
LDMIA r12!, {r0-r11} ; load 48 bytes
STMIA r13!, {r0-r11} ; and store them
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INSTRUCTION FORMAT (LDM/STM)
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USE OF THE S BIT
➤ When the S bit is set in a LDM/STM instruction its
meaning depends on whether or not R15 is in the
transfer list and on the type of instruction.
➤ The S bit should only be set if the instruction is to
execute in a privileged mode.
➤ LDM with R15 in transfer list and S bit set (Mode changes)
➤ If the instruction is a LDM then SPSR_<mode> is
transferred to CPSR at the same time as R15 is
loaded.
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CONTD…
➤ STM with R15 in transfer list and S bit set (User bank
transfer)
➤ The registers transferred are taken from the User
bank rather than the bank corresponding to the
current mode.
➤ This is useful for saving the user state on process
switches.
➤ Base write-back should not be used when this
mechanism is employed.
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CONTD…
➤ R15 not in list and S bit set (User bank transfer)
➤ For both LDM and STM instructions, the User
bank registers are transferred rather than the
register bank corresponding to the current mode.
➤ This is useful for saving the user state on process
switches.
➤ Base write-back should not be used when this
mechanism is employed.
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CONTD…
➤ Base register used to determine where memory access should occur.
➤ 4 different addressing modes allow increment and decrement
inclusive or exclusive of the base register location.
➤ Base register can be optionally updated following the transfer (by
appending it with an ‘!’).
➤ Lowest register number is always transferred to/from lowest
memory location accessed.
➤ These instructions are very efficient for
➤ Saving and restoring context
➤ For this useful to view memory as a stack.
➤ Moving large blocks of data around memory
➤ For this useful to directly represent functionality of the
instructions.
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THANK YOU
11th May 2020
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