Computer Organization
and Architecture
Chapter 3
System Buses
Instruction Cycle - State Diagram
Instruction cycle in a typical computer architecture
Sequence of steps a CPU follows to execute an instruction
The CPU fetches the next Retrieves the operand(s) The result of the operation is
instruction from memory from memory or registers. stored back to memory or a
register.
Performs the operation
The fetched instruction
(e.g., addition, subtraction,
is decoded to understand
logic operations) using the
what needs to be done
fetched operands.
If the instruction involves
Determines the memory storing results, the address
address of the operand(s) for storing is calculated.
needed for the instruction.
Instruction Cycle - State Diagram
Instruction cycle in a typical computer architecture
Sequence of steps a CPU follows to execute an instruction
1. Instruction Fetch: The CPU fetches the 5. Data Operation: The operation (e.g.,
instruction from memory. addition, subtraction, data transfer) is
2. Instruction Operation Decoding: The carried out using the operands.
CPU decodes what the instruction is (e.g., 6. Operand Address Calculation (for
ADD, LOAD, JUMP). It also identifies the result): If the result needs to be stored (like
operand(s) and operation to perform. in a memory location), the CPU calculates
3. Operand Address Calculation: The the address where it will be stored.
CPU calculates the effective address of the 7. Operand Store: The result of the
operand(s), especially if they're in memory operation is stored in memory or a register.
(e.g., based on offset, index, etc.). If there are multiple results, this step may
4. Operand Fetch: The operand(s) are loop back to store each one.
fetched from memory or registers. 8. Instruction Address Calculation
If there are multiple operands, the CPU The CPU calculates the address of the next
may go back and repeat the fetch. instruction.
Instruction Cycle -
State Diagram
•Loops and Conditional Paths
•Instruction Address Calculation: If the instruction is complete, the address of the next
instruction is calculated, and the cycle repeats.
•Multiple Operands/Results: Loops back to fetch more operands or store multiple
results.
•Return for String or Vector Data: In the case of string/vector operations, it may return
to the Data Operation step for repeated processing.
Instruction Cycle - State Diagram
ADD R1, R2, R3
• Instruction Fetch: CPU gets the instruction from memory.
• Instruction Operation Decoding: CPU decodes the instruction: Operation:
ADD, Operands: R2, R3, Destination: R1
• Operand Address Calculation: Since the operands are in registers (not
memory), their addresses are determined (internally, register numbers are
decoded).
• Operand Fetch: Fetch values from R2 and R3. Suppose: R2 = 10 R3 = 20
• Data Operation: Perform the addition: 10 + 20 = 30
• Operand Address Calculation (Store): Calculate where the result should be
stored → R1.
• Operand Store: Store 30 in R1.
• Instruction Address Calculation: CPU calculates the address of the next
instruction and fetches it — the cycle repeats.
What if it's a Memory Operation? For LOAD R1, 0x1000:
• Fetches value from memory address 0x1000 and loads it into R1.
• Operand Address Calculation and Operand Fetch are used to get data from memory (not
just registers).
• Store might not be used unless it's a STORE instruction.
Interrupts
• Interrupts are signals that cause the processor to pause
its current execution, save its state, and jump to a
special routine called an Interrupt Service Routine
(ISR) to handle the event.
1. Program Interrupts (Errors or exceptional conditions during
instruction execution)
– e.g. overflow, division by zero
2. Timer Interrupts (Internal processor timer)
– Generated by internal processor timer
– Used in pre-emptive multi-tasking
3. I/O Interrupts (Signals from I/O devices)
– from I/O controller, completion of I/O or error
4. Hardware failure
– Issues like power failure, memory parity error,
overheating
Why are Interrupts Useful?
• Devices Are Slow Compared to the CPU
— Input/Output (I/O) devices like keyboards, mice, printers, or disk drives
operate much slower than the CPU.
— If the CPU had to wait for each device to complete its task (e.g.,
polling), it would waste valuable processing time.
• Interrupts Improve Efficiency
— Instead of continuously checking (polling) a device to see if it needs
attention, the CPU can focus on other tasks.
— When a device is ready (e.g., I/O complete), it sends an interrupt
signal to the CPU.
— The CPU pauses its current work, services the device, and then
resumes its task.
• Enables Multitasking and Real-Time
Responsiveness
— Interrupts allow the OS to
– Switch between tasks (context switching).
– Handle critical or time-sensitive tasks immediately (like keyboard input or
network packets).
Program Flow Control (1)
• The CPU is
wasting time
during I/O.
• Low efficiency.
• Better CPU utilization. • Even more CPU time
• The CPU continues is used productively.
doing useful work while • Long I/O operations
waiting for I/O to finish. don't block user
programs.
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Program Flow Control (2)
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) - State
Diagram
Multiple Interrupts
• Disable interrupts - Sequential approach
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities - Nested approach
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts - Nested
Time Sequence of Multiple Interrupts
Interconnection Structures
• All the units must be connected
• Interconnection structure:
The collection of paths connecting system
modules
• Different type of connection for different
type of unit
—Memory
Speed: CPU needs faster paths than I/O.
—Input/Output Bandwidth: Memory needs wide highways (e.g., 64-bit
buses).
—CPU Control: Who "talks" first? Protocols like arbitration decide
(e.g., bus masters).
• Design depends on necessary exchanges
between modules
