MODULE V:
ARM 32 BIT MCUS
Shaik Jhani Bhasha
Assistant Professor
CSEN3021:
Dept. of EECE
Microcontrollers and Applications GITAM School of
Technology
Hyderabad
ARM 32 Bit MCUs : Introduction to 16/32-bit
SYLLABUS processors, ARM architecture and organization, ARM /
Thumb programming mode, ARM / Thumb instruction
set, development tools.
ARM Processors can
be divided into:
ARM Classic
Processors,
ARM Embedded
Processors,
and
ARM Application
INTRODUCTION TO 16/32-BIT
PROCESSORS
• A 32-bit processor with an instruction set facilitating a subset
of instructions for 16-bit coding is called a 16/32-bit processor.
MCUs based on 32-bit ARM architecture and 16-bit Thumb
instruction set provide this feature.
• The Thumb instruction set consists of 16-bit instructions that act as a compact
shorthand for a subset of the 32-bit instructions of the standard ARM. Every
Thumb instruction could instead be executed via the equivalent 32-bit ARM
instruction.
TYPICAL
ARM
ARCHITE
CTURE
ARM / TH UM B PRO G RAM M ING
M ODE
•In the ARM state, 17 registers are visible in user mode. One
additional register—a saved copy of Current Program Status Register
(CPSR) that's called SPSR (Saved Program Status Register)—is for
exception mode only. Notice that the 12 registers accessible in Thumb
state are the same physical 32-bit registers accessible in ARM state.
Thus, data can be passed between software running in the ARM state
and software running in the Thumb state via registers R0 through R7.
This is done frequently in actual applications. The biggest register
difference involves the SP register. The Thumb state has unique stack
mnemonics (PUSH, POP) that don't exist in the ARM state. These
instructions assume the existence of a stack pointer, for which R13 is
used. They translate into load and store instructions in the ARM state.
The CPSR register holds the processor mode (user or exception flag),
interrupt mask bits, condition codes, and Thumb status bit. The
Thumb status bit (T) indicates the processor's current state: 0 for ARM
state (default) or 1 for Thumb. Although other bits in the CPSR may be
modified in software, it's dangerous to write to T directly; the results
of an improper state change are unpredictable.
ARM/THUMB
INSTRUCTION
SET • Data processing instructions
arithmetic, logical, comparing
The ARM contains only one instruction set:
the 32-bit set. When it’s operating in the • Branch Instructions
Thumb state , the processor simply expands
the smaller shorthand instructions fetched • Conditional Execution
from memory into their 32-bit equivalents.
• Load Store Instructions
The difference between two equivalent
instructions lies in how the instructions are
fetched and interpreted prior to execution,
not in how they function.
DATA PROCESSING INSTRUCTIONS
Instruction Operation Example
mov rd, n rd = n mov r7, r5 ; r7 = r5
add rd, rn, rd = rn + add r0, r0, #1 ; r0 =
n n r0 + 1
sub rd, rn, rd = rn - n sub r0, r2, r1 ; r0 = r2
n + r1
cmp rn, n rn - n cmp r1, r2 ; r1 - r2
BRANCH INSTRUCTIONS
• b label ; pc = label
• bl label ; pc = label, lr = addr of next
instruction
CONDITIONAL INSTRUCTIONS
Mnemonic Condition
EQ Equal
NE Not Equal
CS Carry Set
CC Carry Clear
VC Overflow Clear
VS Overflow Set
PL Positive
MI Minus
HI Higher Than
HS Higher or Same
LO Lower Than
LS Lower or Same
GT Greater Than
GE Greater Than or Equal
LT Less Than
LE Less Than or Equal
LOAD STORE INSTRUCTIONS
• ldr rd, addressing ; rd = mem32[addr]
• str rd, addressing ; mem32[addr] = rd
• ldrb rd, addressing ; rd = mem8[addr]
• strb rd, addressing ; mem8[addr] = rd
ARM DEVELOPMENT TOOLS
• • ARM C Compiler
• • ARM Assembler
• • Linker
• • ARMsd
• • ARMulator
• • ARM Development Board
• • Software Toolkit
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