CPE 519

Digital Design with VHDL

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 1

What is VHDL ?
• VHDL stands for VHSIC Hardware Description Language
• VHSIC =Very High-Speed Integrated Circuit
• Initialized by US DoD as a sponsored program
• Standardized as IEEE 1076-1987 in 1987
• Revised in 1993 (used in this course)
• Other HDLs: Verilog and ABEL
• DoD requires that VHDL descriptions be delivered for all
ASICs.
• every major CAD vendors supports VHDL

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 2

HDLs - Motivation
• Increased productivity
• shorter development cycles, more features, but........
• still shorter time-to-market, 10-20K gates/day/engineer
• Flexible modelling capabilities.
• can represent designs of gates or systems
• description can be very abstract or very structural
• top-down, bottom-up, complexity hiding (abstraction)
• Design reuse is enabled.
• packages, libraries, support reusable, portable code
• Design changes are fast and easily done
• convert a 8-bit register to 64-bits........
• four key strokes, and its done!
• exploration of alternative architectures can be done quickly
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 3
HDLs – Motivation…
• Use of various design methodologies.
• top-down, bottom-up, complexity hiding (abstraction)
• Technology and vendor independence.
• same code can be targeted to CMOS, ECL, GaAs
• same code for: TI, NEC, LSI, TMSC....no changes!
• Enables use of logic synthesis which allows a
investigation of the area and timing space.
• ripple adder or CLA?, How many stages of look ahead?
• HDLs can leverage software design environment tools.
• source code control, make files
• Using a standard language promotes clear
communication of ideas and designs.
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 4
What are HDLs?
• A Hardware Description Language (HDL) is a programming language used to
model the intended operation of a piece of hardware.
• An HDL can facilitate:
• abstract behavioural modeling
• no structural or design aspect involved
• hardware structure modelling
• a hardware structure is explicitly implied
• In this class we will use an HDL to describe the structure of a hardware design.
• When we use an HDL, we will do so at what is called the Register Transfer
Language level (RTL).
• At this level we are implying certain hardware structures when we understand apriori.
• When programming at the RTL level, we are not describing an algorithm which some
hardware will execute, we are describing a hardware structure.
• We must know beforehand the structure we want to build, before you
describe it in an HDL

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 5

VHDL Provides
• Portability
• Interoperability across vendors
• Code reuse
• Distributed design
• Reliable design process
• Minimized design time and cost

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 6

Programming Languages vs. HDLs
• Procedural programming languages (C or Pascal) typically
provide procedures for
• Performing a computation (e.g. matrix multiplication)
• Manipulating data (e.g. sorting)
• Hardware description language is used to describe a
digital system
• Simulate the behavior of the system without actually
constructing the system
• Synthesis compilers can use the description to actually build a
digital system implementing this behavior
• VHDL is primarily used for digital system design

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Why Describing Systems ?
• Design specification
• Unambiguous definition of components and interfaces in a
large design.

• Design Simulation
• Verify system/subsystem/chip performance prior to
implementation

• Design Synthesis
• Automated generation of hardware implementing the digital
system

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Design Flow: Top-down approach
Requirements

Functional Behavioral simulation

Design
Memory, Register RTL Simulation Validation
Adder etc. Transfer Level
Design
Logic simulation, Verification
Logic Design Fault Simulation

Timing simulation
gates Circuit Design Circuit Analysis

transistor Physical Design Design Rule Checking

Description for Manufacture

ASIC Design Process 9

Levels of Abstraction
• Design tools support to perform simulation at each level
• These simulations are for anticipating behavior, physical
properties, and performance of the circuit

• Simulation at lower levels offers more accurate predictions, but

takes longer.

• If design errors are discovered at lower levels, changes in the

design to correct faults may be expensive longer
development times

• Having simulation capability at different level helps detect and

correct the design errors at earlier stages

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 Synthesis Design Flow for FPGA
Requirements

VHDL Model Functional

Design
Register
VHDL Model
Transfer Level
Design

Logic Simulation Synthesis

Behavioral
Simulation
Place and Route
(VHDL)

Timing
Extraction More realistic
timing values

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Summary
• HDL for describing digital systems
• specification
• simulation
• synthesis
• Description at various levels of abstraction
• system, architectural, RTL, logic, gate, etc.
• VHDL integrates point tools into a cohesive design process
• VHDL is independent of technology
• faster time-to-market

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 LOGIC OVERVIEW

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 13

Combinational Logic
• Basic Gates

A A
C C
B B

AND: C = AB OR: C = A+B

A
A C C
B

NOT: C = A’ XOR: C = A  B

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Truth Tables and Algebraic Expressions
• Full Adder
X Y Cin Cou Sum
t
0 0 0 0 0
X
FULL Cout 0 0 1 0 1
Y ADDER Sum 0 1 0 0 1
Cin
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Sum = X ’ Y ’ Cin + X ’ Y Cin ’ + X Y ’ Cin ’ + X Y Cin

Cout = X ’ Y Cin + X Y ’ Cin + X Y Cin ’ + X Y Cin

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 Minterm and Maxterm Expansions
• Minterm expansion
Sum = X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin =  m(1,
2, 4, 7)
Cout = X’ Y Cin + X Y’ Cin +X Y Cin’ + X Y Cin =  m(3, 5, 6, 7)

• Maxterm expansion
Sum = (X+Y+Cin)(X+Y’+Cin’)(X’+Y+Cin’)(X’+Y’+Cin) =  M(0,3, 5, 6)

Cout = (X+Y+Cin)(X+Y+Cin’)(X+Y’+Cin)(X’+Y+Cin) =  M(0,1, 2, 4)

• Minterm expansion  Maxterm expansion

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Algebraic Simplification 1
1.Combining Terms (XY + XY’=X)
• ABC’D’ + ABCD’ = ABD’ (C + C’) = ABD’

• Cout = X ’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin

= X’ Y Cin + X Y’ Cin + X Y Cin’ + XY Cin + X Y Cin + X Y Cin
= X’ Y Cin + X Y Cin + X Y’ Cin + X Y Cin + X Y Cin’ + XY Cin
= Y Cin + X Cin + XY
2.Eliminating Terms
• A’B + A’BC = A’B
• Consensus theorem: XY + X’Z + YZ = XY + X’Z

CBD + C’A’B + DA’B = CBD + C’A’B + BDA’B = CBD + CA’B’

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Algebraic Simplification 2
• Eliminating Literals
• X + X’Y = X + Y
• A’B + A’B’C’D’ + ABCD’ = A’(B + B’C’D’) + ABCD’
= A’(B + C’D’) + ABCD’ = A’B + A’C’D’ + ABCD’
= B (A’ + ACD’) + A’C’D’
= B (A’ + CD’) + A’C’D’ = A’B + BCD’ + A’C’D’
• Adding Redundant Terms
• Adding XX’, multiplying by (X+X’),
• Adding YZ to XY + X’Z or adding XY to X
• AB + AD + A’C’ + DB’C’ = AB + DC’B’ + AD + A’C ’ + DC ’
= AB + AD + A’C’ + DC ’ = AB + AD + A’C’

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Duality Principle
• Important property of Boolean algebra
• If x + 0 = x then x · 1 = x

x+x=x x·x = x
x + x’ = 1 x · x’ = 0
x+1=1 x·0=0
(x + y + …)’ = x’ · y’ … (x · y · …)’ = x’ + y’ + …
x+x·y=x x ·(x+y) = x
xy + x’ z + y z = xy + (x+y)(x’+z)(y+z) = (x+y)
x’ z (x’+z)
(x+y)(x’+z) = x z + x’ xy + x’ z = (x+z) (x’+y)
y

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Exclusive OR ( XOR)
• Some rules
• X0=X
• X  1 = X’
• XX=0
• X  X’ = 1
• Commutative, associative, and distributive laws hold.
• X  Y = X’Y + XY’
• (X  Y)’ = X  Y’ = X’  Y = XY + X’Y’

• Sum = X’ Y’ Cin + X’ Y Cin’ +X Y’ Cin’ + X Y Cin

= (X’ Y’ + X Y) Cin + (X’ Y + X Y’) Cin’
= (X  Y)’ Cin + (X  Y) Cin’
= X  Y  Cin

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Karnaugh Maps (1)
• F = A’B’C’D’ + AB’C’D’ + A’B’CD’ + AB’CD’

AB
CD 00 01 11 10

00 1 1

01

11

10 1 1

• F = A’B’C’D’ + AB’C’D’ + A’B’CD’ + AB’CD’ = B’D’

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Karnaugh Maps (2)
• F = A’B’C’D’ + AB’C’D’ + A’B’CD’ + AB’CD’

AB
CD 00 01 11 10

00 1 0 0 1

01 0 0 0 0

11 0 0 0 0

10 1 0 0 1

• F = (B+D)’ = B’D’ (DeMorgan’s Law)

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Karnaugh Maps (3)
AB
CD 00 01 11 10

00 1 X 0 1

01 1 1 0 0

11 0 1 1 1

10 1 0 X 0

• F = A’C’ + A’B’D’+ ACD + BCD or

• F = A’C’ + A’B’D’+ ACD + A’BD

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Designing with NAND and NOR gates - 1
• In many technologies, implementation of NAND or NOR
gates is easier than that of AND or OR gates
• Any logic function can be realized using only NAND gates or
only NOR gates

A A
B
C  B
C

NAND: C = (AB)’ = A’+B’

A
A
C  B
C
B
NOR: C = (A+B)’ = A’B’

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Designing with NAND and NOR gates - 2
• Conversion of AND-OR network to NAND gates

A
B
E=AB+CD
C
D

A
B
E=((AB)’(CD)’)’=AB+CD
C
D

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Designing with NAND and NOR gates - 3
• Conversion of AND-OR Network to NOR gates

A
B
E=(A+B)(C+D)
C
D

A
B
E=((A+B)’+(C+D)’)’=(A+B)(C+D)
C
D

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Designing with NAND and NOR gates - 4
• Conversion of AND-OR network to NAND gates

A
B
C
D F
E


A
B
C
D F
E

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Hazards in Combinational Networks - 1
• Unwanted switching transients
• Occur when different paths from input to output have different
propagation delays

• 1-hazard : network output may momentarily go to 0 when it

should remain a constant 1

• 0-hazard : network output may momentarily go to 1 when it

should remain a constant 0

• Dynamic-hazard : when the output is supposed to change (1-0

or 0-1), the output may change three times (e.g. 1-0-1-0)

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Flip-Flops
D Flip-Flop D Q Q+
0 0 0
D Q 0 1 0
DFF
clk Q’ 1 0 1
1 1 1

J K Q Q+
0 0 0 0
Clocked JK Flip-Flop 0 0 1 1
0 1 0 0
J Q
JK 0 1 1 0
clk
FF 1 0 0 1
K Q’
1 0 1 1
1 1 0 1
Q = JQ’ + K’Q 1 1 1 0

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Latches - 1
S-R Latch
S R Q Q+
0 0 0 0
S 0 0 1 1
Q 0 1 0 0
0 1 1 0
1 0 0 1
Q’ 1 0 1 1
R
1 1 0 -
1 1 1 -

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Latches - 2
Gated D Latch

D G D Q Q+
0 0 0 0
G
0 0 1 1
0 1 0 0
Q
0 1 1 1
1 0 0 0
1 0 1 0
D 1 1 0 1
1 1 1 1

Q+ = DG + G’Q + DQ

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Mealy Sequential Network Design
General Model of Mealy Sequential Design

Inputs (X)
Outputs (Z)
Combinational
Network Next
state State state
Reg.
clk

Outputs depend on both present state and present

input
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Moore Machine
• The output is only function of the present state,
independent of the input.
• Input determines the next state.

Inputs (X)
Outputs (Z)
Combinational
Network Next
state State state
Reg.
clk

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Setup and Hold Times 1
• For an ideal D flip-flop
• If the D input changes at exactly the same time as the active
edge of the clock, flip-flop operate correctly

• In reality
• The D input must be stable for a certain amount of time before
the active edge of the clock; setup time
• Furthermore, D must be stable for a certain amount of time
after the active edge of the clock; hold time

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 Setup and Hold Times 2
tsu th

clock

Q tplh tphl

• In shaded interval above D may be changed

• Otherwise, it cannot be determined whether the flip-flop will
change state
• Even worse, the flip-flop may malfunction and output a short
pulse and even go into oscillation
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Synchronous Design
• A clock is used
• To synchronize the operation of all flip-flops, registers, and
counters in the system
• All state changes occur following the active edge of the clock
• The clock period must be long enough so that all flip-flop and
register inputs will have time to stabilize before the next active
edge of the clock

Data In
clock
Control Signals
Control Control Data
Inputs Section Section
Condition Signals
Data Out

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Tristate Logic and Buses
• Tristate buffers
B B B B

A C A C A C A C

B A C B A C B A C B A C
0 0 Hi-Z 0 0 Hi-Z 0 0 0 0 0 1
0 1 Hi-Z 0 1 Hi-Z 0 1 1 0 1 0
1 0 0 1 0 1 1 0 Hi-Z 1 0 Hi-Z
1 1 1 1 1 0 1 1 Hi-Z 1 1 Hi-Z

• Hi-Z : high-impedance which is equivalent to an open

circuit.
• We use tristate buffers to connect the outputs of more
than one gates or flip-flops. 37
Tristate Bus
Eni
Input 8 Tristate bus
Data
8
Ena Enb Enc

Lda Reg. A Ldb Reg. B Ldc Reg. C

clock

• If Enb = Ldc = 1 (all others 0), then the data in register B will be
copied into register C when the active edge of the clock occurs.
• If Eni = Lda = Ldc = 1 then the input data will be loaded in
registers A and C when the registers are clocked.

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