UNIT-4
Processor: Building a datapath
and Control
Prepared by
Mrs.E.VIDHYA-AP/ECE
Components of a
Computer
Process
Datapath or Control
Components of Component of the
the processor processor that
that perform commands the
arithmetic datapath,
operations and memory, I/O
holds data devices according
to the
instructions of the
memory
BASIC
PERFORMANCE
CPU Time Instruction Count CPI Clock
Cycle Time
CPU performance factors
Instruction count
• Determined by Instruction Set Architecture and
compiler
CPI and Cycle time
• Determined by implementation of the processor
Building a datapath
Datapath
Elements that process data and
addresses in the CPU
• Memories, registers, ALUs, …
We will build a MIPS datapath
incrementally
considering only a subset of
instructions
To start, we will look at 3
elements
A memory unit to store instructions of a
program and supply instructions given
an address
Needs to provide only read access
(once the program is loaded).
No control signal is need.
PC (Program Counter or Instruction address
register) is a register that holds the address
of the current instruction
A new value is written to it every clock
cycle. No control signal is required to
enable write
Adder to increment the PC to the
address of the next instruction
An ALU permanently wired to do only
No extra control signal
addition.
required
Datapath portion for
Instruction Fetch
Increment by
4 for next
32‐bit instruction
register
Types of Elements in the
Datapath
State element:
A memory element, i.e., it contains
a state
E.g., program counter, instruction
memory
Combinational element:
Elements that operate on values
E.g. adder,ALU
R-FormatA LU
Instructions
Register file: A collection of the
registers
Any register can be read or written by
specifying the number of the register
Contains the register state of the
computer
Read from register file
2 inputs to the register file specifying the
numbers
• 5 bit wide inputs for the 32 registers
2 outputs from the register file with the read
values
• 32 bit wide
For all instructions. No control required.
Write to register file
1 input to the register file specifying the
number
• 5 bit wide inputs for the 32 registers
1 input to the register file with the value to be
written
• 32 bit wide
Only for some instructions. RegWrite control
ALU
Takes two 32 bit input and produces a 32
bit output
Also, sets one-bit signal if the results is 0
The operation done by ALU is controlled
by a 4 bit control signal input.This is set
according to the instruction
Data transfer
instructions
Compute the memory address by
adding the value in base register and
the 16 bit offset
need the ALU
Calculate address using 16-bit offset
• Use ALU, but sign-extend offset
Write to or read from register
need the register file
Two additional units – data memory
and sign unit extension
Data memory
State element with
• input for address and data to be written
• output for read result
Data memory
Separate control for read and write
Control for read is required because
reading from invalid address can lead to
problems
Sign-extension unit takes a 16 bit
input and extend it to a 32 bit
Composing the Elements for R-
type and data transfer
instructions
A simple data path that does an
instruction in one clock cycle
Each datapath element can only do one
function at a time
Hence, we need separate instruction
and data memories
Use multiplexers where alternate data
sources are used for different
instructions
Multiplexers
An ALU might need input from
Two registers
Or one registers and one immediate field
(or offset)
To choose correctly from multiple sources, a
hardware element called multiplexor is
used with appropriate control signals
20
Multiplex
ers
The data written to registers may
come from
Data memory
Or ALU
To choose correctly from multiple
sources, a hardware element called
multiplexor is used with appropriate
control signals
R-Type/Load/Store
Datapath
Branch
Just re‐
Instructions
routes
wires
Sign‐bit wire
replicated
Composing all elements
together
Instruction fetch datapath
Datapath for R-type and memory
instructions
Datapath for branches
Need an additional multiplexor to
select the sequential address after
branch or the branch target address
to be written to the PC
Full
Datapath
