6 Rtl Verification Jobs nearby Vapi

Job Description Role Overview: As a Graduate Engineer at PulseWave Semiconductor, located in Ahmedabad/Bangalore, you will be responsible for VLSI design, verification, and FPGA services. Your day-to-day tasks will include RTL coding, testbench development, system-level testing, and seamless system integration. Key Responsibilities: - Perform RTL coding for VLSI design projects - Develop testbenches for verification purposes - Conduct system-level testing to ensure functionality - Integrate systems seamlessly for optimal performance Qualification Required: - Bachelor's or Master's degree in Electronics Engineering or related field - Knowledge of SV UVM and industry-standard EDA tools is an added advantage - Strong problem-solving and analytical skills - Excellent written and verbal communication skills - Ability to work effectively in a team environment,

You have a great opportunity as an RTL/FPGA Design Engineer with a minimum of 3-7 years of experience. Your role will involve RTL programming using Verilog/System Verilog or VHDL, knowledge of the complete FPGA Design Development flow, hands-on experience with FPGA Development Tools like Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will be responsible for functional verification using Verilog/System Verilog or VHDL, RTL Code Optimization to meet timings and fit on-chip resources, supporting all phases of FPGA based product development activities, system architecture design, and testing and troubleshooting of hardware. **Key Responsibilities:** - RTL programming using Verilog/System Verilog or VHDL. - Knowledge of the complete FPGA Design Development flow. - Hands-on experience with FPGA Development Tools like Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. - Functional verification using Verilog/System Verilog or VHDL. - RTL Code Optimization to meet timings and fit on-chip resources. - Support all phases of FPGA based product development activities. - System Architecture Design. - Testing and troubleshooting of hardware. **Qualification Required:** - BE/B. Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. - ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. - Experience with Verilog/SystemVerilog or VHDL for design and verification. - In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. - Ability to develop small blocks of IP from scratch and perform basic functional verification. - Familiarity with protocols like SPI, I2C, UART and AXI. - Understanding of standard/specification/application for IP design or system design. - Knowledge of tools like Altera Quartus II Tool, Questasim, Modelsim, Xilinx ISE, Vivado, Microsemi libero. - Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash. You will need to be self-motivated, able to work effectively with global teams, collaborate well in a team-oriented environment, prioritize tasks effectively in a fast-paced setting, and have strong analytical and problem-solving abilities. Your passion for writing clean and neat code following coding guidelines will be a great asset in this role.,

You will be joining the DDR Memory Controller IP development team at Cadence as an RTL Design Engineer. Your role will involve designing and supporting the RTL of the DDR Memory Controller solution, which includes supporting leading DDR memory protocols such as DDR4/LPDDR4. Your responsibilities will include working with existing RTL, adding new features, ensuring clean customer configurations during verification regressions, supporting customers, and ensuring compliance with LINT and CDC design guidelines. Key Responsibilities: - Design and support RTL of DDR Memory Controller solution - Add new features to existing RTL - Ensure clean customer configurations in verification regressions - Support customers and ensure design compliance with LINT and CDC guidelines Qualifications Required: - BE/B.Tech/ME/M.Tech in Electrical / Electronics / VLSI - Experience as a design and verification engineer with a focus on RTL design and development - Proficiency in Verilog for RTL design - Experience with System Verilog and UVM based environment usage / debugging - Desired experience with AXI3/4 - Highly desirable experience with DDR Memory controller and protocol - Prior experience in RTL design and implementation of complex protocols - Experience in IP development teams would be an added advantage Cadence is a company that values innovation and leadership, where you will have the opportunity to work on impactful technology solutions. Join us in solving challenges that others can't.,

As an experienced FPGA design engineer with 5+ years of experience, you will be responsible for implementing control logic state machines and DSP algorithms in FPGA fabric for high throughput systems. Your role will require excellent troubleshooting and debug skills for both simulation and in-circuit scenarios. Your expertise should include: - Excellent knowledge of digital design with multiple clock domains - RTL design proficiency in Verilog and System-Verilog - Creating micro-architecture from high-level specifications - Functional simulation using ModelSIM or similar tools - FPGA design and synthesis techniques including map and route flow, pin assignments, attribute assignments, resource fixing, and design partitioning - Targeting designs for Intel(Altera) or Xilinx FPGAs using Quartus Prime or Vivado - IP creation and parametrization with Vivado or Quartus - Debugging using ChipScope/SignalTap and lab bench oscilloscopes/protocol analyzers - Knowledge of static timing analysis and timing closure using SDC - Collaborating with cross-functional global teams of hardware designers, software engineers, and verification and validation engineers - Leading teams to successful project completion within deadlines - Excellent problem-solving skills It would be beneficial if you also have expertise in: - TCL scripting and Python - Transceivers and PHY - Power estimation and resource utilization estimation - Soft-processor cores like Microblaze or Nios-II - Understanding of Digital Signal Processing concepts - Proficiency in Matlab or Python for algorithm design - Knowledge of embedded systems and C/C++ About A&W Engineering Works: A&W Engineering Works is dedicated to developing and deploying innovative solutions to real-world problems. The company specializes in developing complete systems from front-end sensors to back-end applications, covering analog, digital signal processing, and algorithmic data and control paths. The team at A&W Engineering Works comprises experts in hardware, software, mechanical, and system development, enabling them to address challenging problems with unique and innovative development techniques for quick prototyping and efficient production. To apply for this position, please email your resume and cover letter to [email protected] with the job title in the subject line.,

As a Senior Engineer / Technical Lead (FPGA) at our company, your role will involve: - Using hardware such as oscillator and logic analyzers for hardware debugging - Demonstrating a good understanding of digital electronics and design practices - Exhibiting a strong sense of ownership, passion, fast learning ability, analytical mindset, and pursuit of perfection - Showcasing excellent interpersonal, communication, collaboration, and presentation skills We are looking for candidates with the following qualifications: - Strong VHDL/Verilog Programming skills - In-depth knowledge of RTL design, FPGA design, and FPGA design tools - Proficiency in the complete FPGA development flow from logic design, place & route, timing analysis closure, simulation, verification, and validation - Experience with Xilinx/Intel/Lattice/Microchip FPGA families and corresponding development tools - Familiarity with verification/simulation tools such as Modelsim/Questa-sim - Strong troubleshooting and debugging skills for FPGA implementations on hardware boards - Experience in debugging HW/SW issues and utilization of equipment/tools like oscilloscope, logic analyzer, Chipscope/ILA/Signal Tap - Ability to comprehend synthesis reports, conduct timing analysis, and write FPGA design constraints - Hands-on experience with communication protocols (UART/I2C/SPI, etc.) and bus interfaces (AMBA/AXI, etc.) In addition to the technical aspects of the role, the job is based in Pune and Ahmedabad, specifically in IN-GJ-Ahmedabad, India-Ognaj (eInfochips). This is a full-time position in the Engineering Services category.,

As a Senior Physical Design Engineer with 6 years of experience, you will lead the physical implementation of advanced semiconductor projects. Your role will be crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. **Key Responsibilities:** - Provide technical guidance and mentoring to physical design engineers. - Interface with front-end ASIC teams to resolve issues. - Implement low-power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. - Work on timing closure for DDR2/DDR3/PCIE interfaces. - Utilize a strong background in ASIC Physical Design including floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Use extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools. - Demonstrate expertise in scripting languages like PERL, TCL. - Apply strong Physical Verification skill set. - Conduct Static Timing Analysis in Primetime or Primetime-SI. - Communicate effectively with written and oral skills, documenting plans clearly. - Collaborate with different teams and prioritize work based on project needs. **Qualifications Required:** - Ability to perform top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks. - Experience with 65nm or lower node designs and advanced low power techniques. - Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification. - Bachelors or Masters degree in electronics engineering or related field. This job also requires familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, Mentor Calibre, and knowledge of low-power design techniques and implementation.,

As an RTL Designer in the DSP processor team at Qualcomm India Private Limited, your main responsibility will be to develop RTL for multiple logic blocks of a DSP core. You will work on various frontend tools to check for linting, clock domain crossing, synthesis, etc. Additionally, you will collaborate with the physical design team on design constraints and timing closure, work with the power team on power optimization, and collaborate with the verification team on test plan, coverage plan, and coverage closure. **Key Responsibilities:** - Develop RTL for multiple logic blocks of a DSP core - Run various frontend tools to check for linting, clock domain crossing, synthesis, etc. - Work with the physical design team on design constraints and timing closure - Collaborate with the power team on power optimization - Collaborate with the verification team on test plan, coverage plan, and coverage closure **Qualifications Required:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field Please note that Qualcomm India Private Limited is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process. If you require any accommodations, you may contact Qualcomm at disability-accomodations@qualcomm.com. Qualcomm expects all its employees to comply with applicable policies and procedures, including those related to the protection of company confidential information and other proprietary information. If you are an individual seeking a job at Qualcomm, please note that staffing and recruiting agencies are not authorized to use Qualcomm's Careers Site to submit profiles, applications, or resumes. Unsolicited submissions from agencies will not be accepted. For more information about this role, you can contact Qualcomm Careers.,

As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. Your role involves developing testbenches, building reusable components, and ensuring complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze waveforms (using DVE/SimVision), track bugs, and maintain bug databases (JIRA, Bugzilla) Qualifications Required: - B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design Please note that the job type is Full-time and Permanent, with a Day shift schedule and the work location is in person.,

Role Overview: At QpiAI, we are looking for a skilled and motivated Hardware Verification Engineer to join our Hardware team. You will play a crucial role in creating models and test plans to verify the functionality and performance of in-house chip designs. As part of our team, you will be involved in understanding the design, defining the verification scope, developing the verification infrastructure, and ensuring the correctness of the design. Key Responsibilities: - Create models and test plans for verifying functionality and performance of in-house chip designs - Understand the design, define the verification scope, develop the verification infrastructure, and verify the correctness of the design Qualifications Required: - Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science or related field; advanced degrees (MS, PhD) are a plus - 2+ years of relevant work experience - Proficiency in verification languages such as System Verilog or equivalent, and methodologies like UVM or equivalent - Experience with verification tools like VCS and Verdi - Good debugging and problem-solving skills (Note: No additional details about the company were provided in the job description),

You are invited to join our team as a skilled Hardware Verification Engineer based in Hyderabad. In this role, you will be instrumental in contributing to the development of cutting-edge hardware solutions. Your primary responsibilities will include developing and maintaining System Verilog /UVM test-benches at various levels, defining test plans and specifications, engaging in verification environment architecture, collaborating with design teams, generating comprehensive documentation, performing hardware testing, and contributing to FPGA-based verification. Key Responsibilities: - Develop and maintain System Verilog /UVM test-benches at block, subsystem, and top levels. - Define and drive test plan, test specification, and test execution for complex hardware modules. - Engage in verification environment architecture and methodology development. - Collaborate with design teams to ensure functional correctness, coverage, and debugging of RTL code. - Generate and maintain comprehensive documentation including user guides, test plans, test specifications, and test reports. - Perform hardware testing using test equipment such as logic analyzers, traffic generators, and signal analyzers. - Contribute to FPGA-based verification using Xilinx tools and technology. Required Skills & Experience: - Strong experience in SystemVerilog and UVM-based verification. - Proficiency in verification of standard protocols such as Ethernet, PCIe, SPI, I2C, USB. - Hands-on experience with hardware test equipment like logic analyzers, oscilloscopes, and traffic generators. - Experience with Xilinx FPGA verification and toolchains. - Strong debugging skills at device, signal, and board levels. - Familiarity with scripting languages like Perl, Python, or TCL. - Excellent analytical, problem-solving, and communication skills. - Ability to work effectively in a collaborative and fast-paced development environment. Additional Relevant Skills (Preferred/Bonus): - Experience with code and functional coverage collection and analysis tools (e.g., VCS, Questa, Incisive). - Proficiency with constraint random verification and assertion-based verification (ABV). - Familiarity with simulation acceleration, emulation (e.g., Palladium, Veloce), or formal verification tools. - Understanding of SoC architecture, DMA, memory controllers, and bus interfaces (AXI, AHB, APB). - Exposure to version control systems such as Git, Perforce, and CI/CD verification automation. - Experience working in Agile/Scrum environments. - Exposure to cloud-based verification environments or remote simulation tools. - Familiarity with coverage-driven verification (CDV) and verification management tools like JasperGold, Specman, or Cadence vManager. If you choose to join us, you will have the opportunity to work on next-generation products in a technically driven team, with growth opportunities in both frontend and backend design flows. You will also enjoy a supportive work environment with access to advanced labs and equipment.,

Role Overview: As a Design Verification Engineer at Architect Labs, you'll redefine the hardware design and verification process, methodology, and tools using proprietary AI models and systems. You will be responsible for building and curating high-quality RTL and verification datasets for AI training and evaluation. Your tasks will include working on test-benches, coverage analysis, assertion coding, debug-friendly measurements, curation, and labeling of AI-generated collateral. Key Responsibilities: - Create detailed test plans based on design specifications - Specify and build a UVM-based validation infrastructure for POC designs - Develop directed and random test cases to thoroughly test the design - Execute simulations and analyze results to identify and debug RTL/Verif bugs - Analyze simulation logs, coverage reports, waveform traces, and generate convergence data for AI models - Label, categorize verification outcomes (pass/fail, assertion hits, coverage, etc.) - Identify, classify, tabulate, and generate analytics for DV bug/fix patterns - Help in prompt-tuning, generating rules, and guardrails for RTL coding agents and models - Collaborate with ML engineers to build evaluation datasets, internal benchmarks, and evaluate model behavior and performance on verification tasks Qualifications Required: - Bachelor's (or more) degree; 3+ years of experience in design/IP verification flows - Proficiency in System Verilog & standard verification methodologies (UVM, OVM) - Experience with simulation and debugging tools like VCS, Xcelium, Verdi, etc. - Experienced in test-bench, stimuli, checkers, score-boards, and monitors development - Familiarity with coverage methodology, signature, and bug analysis - Scripting skills in Python/Perl for test automation - Familiarity with SoC integration and design principles Additional Details of the Company: Uplers" goal is to make hiring reliable, simple, and fast. They aim to help talents find and apply for relevant contractual onsite opportunities and progress in their careers. Uplers will provide support for any grievances or challenges faced during the engagement. There are multiple opportunities available on the portal, and based on the assessments cleared, candidates can apply for them. If you are looking for a new challenge, a great work environment, and an opportunity to advance your career, don't hesitate to apply today as they are waiting for you.,

As a Senior RTL Design | Senior Design Verification Engineer at Marquee Semiconductor, you will be responsible for Spec to RTL sign-off with Microarchitecture, RTL Design, and Verification. You should have the ability to work independently on verification, from Feature extraction to Constrained Random Tests, ensuring full functional and code coverage. Experience with Low-power verification is considered a significant advantage. Qualifications required for this role include a degree in EE/ECE/CS. The position is based in Bangalore, and it is an on-site role. Please send your resume to resume@marqueesemi.com with the subject line Senior RTL Design | Design Verification Engineer Bangalore.,

You will be responsible for defining micro-architecture specifications and detailed designs for interconnects (NoCs/NICs) and related IPs based on system-level use cases. You will collaborate with SoC, verification, physical design, floorplan, and core teams to develop optimal NoC topology for area and performance. Additionally, you will innovate partitioning strategies for implementation-friendly interconnect designs, own coherent interconnect solutions (Full/IO) across cores and subsystems, ensure interconnect meets performance targets, and validate assumptions with the silicon validation team. Furthermore, you will partner with third-party NoC technology providers to shape future interconnect technology for NXP products. Qualifications required for this position are: - BTech/MTech/Ph.D. in Electrical/Computer Engineering or similar disciplines with 5-10 years of relevant experience. - Strong understanding of interconnect protocols: AHB, AXI, ACE, ACE-Lite, NoC concepts. - Familiarity with tools like Arteris FlexNoC, ARM Socrates. - Proficiency in scripting languages: PERL/Python. - Solid knowledge of Digital Design and RTL development; hands-on experience with SoC Design and Verilog RTL coding. - Working knowledge of Synthesis, DFT, verification, and silicon debug. - Experience with Lint, CDC, PLDRC, CLP, etc. If you join us, you will have the opportunity to: - Work on cutting-edge semiconductor solutions - Be part of a collaborative, growth-driven team - Have opportunities for learning and career advancement Please send your resume to vinayak_shrivastava@yahoo.com or dhruv.arya@hotmail.com.,

Role Overview: You will play a crucial role in shaping the future of hardware experiences as a part of the team working on custom silicon solutions for Google's direct-to-consumer products. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services, aiming to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Key Responsibilities: - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Conduct Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up - Create tools/scripts to automate tasks - Track progress and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience - At least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog - Experience in the design and development of Security or Audio blocks - Experience with a scripting language like Perl or Python - Familiarity with DSI2 or MIPI C/D Phy - Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science (ideally) - Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT (preferred) - Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture (beneficial),

As an IP Level Verification Engineer at our company, you will be responsible for independently owning the verification of IP level modules end to end with continuous enhancements. Key Responsibilities: - Verification of IP level modules - Continuous enhancements of verification processes Qualifications Required: - Minimum Qualifications: Verification aptitude, Expertise in SV-UVM, Coverage Closure, RTL debug till root causing, Low Power Verification/UPF, GLS, Assertions based verification, DPI, Testbench building - Familiarity with bus protocols like AHB, AXI, ARM based system architecture, emulation (ex: Veloce), Scripting language like Perl - Excellent problem-solving skills - Strong communication and teamwork skills - Preferred Qualifications: Formal Verification concepts and working knowledge, C/C++, working knowledge on camera are a plus In addition to the above, our company values education and requires candidates to have a BE/BTech/ME/MTech/MS in Electrical Engineering and/or Electronics, Vlsi from a reputed university with preferably distinction. If you find this opportunity exciting and have the required qualifications, we welcome you to apply. Please send your resumes to hr@smartvlsi.com. (Note: Location for the job can be in Bangalore, Hyderabad, Chennai, or Delhi.),

As a Design and Verification Trainer, you will be responsible for providing guidance and support to budding engineers in the areas of RTL design, functional verification, and VLSI concepts. You will utilize your practical experience in front-end design and verification methodologies to effectively convey technical knowledge in an organized, engaging, and articulate manner. Key Responsibilities: - Demonstrating a strong command over hardware description languages such as Verilog and SystemVerilog - Utilizing a deep understanding of verification methodologies including UVM and SystemVerilog Assertions - Proficiency in simulation and debugging tools like Synopsys VCS, VERDI, and Spyglass - Applying expertise in scripting, analytical thinking, and problem-solving skills to deliver high-quality training sessions Qualifications Required: - A Master's degree in Electronics or VLSI Design, equivalent qualifications will also be considered - Prior experience in curriculum development, instructional design, and teaching is highly desirable - Effective communication and presentation skills to convey complex concepts to learners - Previous exposure to the VLSI design or semiconductor industry and proficiency in Design Thinking will be beneficial If you are passionate about sharing your knowledge and expertise in design and verification, possess the requisite qualifications and skills, we invite you to join our team as a Design and Verification Trainer.,

As an experienced Verification Engineer with 8 to 15 years of experience, you should have a good understanding of verification concepts and techniques. Your knowledge of Verilog/System Verilog and UVM should be very strong. You will be responsible for verifying IPs related to different applications, with a focus on Power aware verification and Gate level verification. Understanding the Full-chip Verification requirements and having knowledge of industry standard protocols are essential for this role. Key Responsibilities: - Verification for complex IPs and successfully closing the Verification to meet challenging milestones - Strong knowledge of AXI4/AXI5 protocol and understanding of Coherency rules in ACE and ACE5 - Experience with architecting BFMs/VIPs and capable of handling a team of 3-4 engineers - IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation - Supporting in building verification infrastructure at the chip level as per the requirements - Capable of handling multiple areas of IP Verification including RTL, Power Aware, and Gate Level Verification Qualifications Required: - 8 to 15 years of experience in Verification Engineering - Strong knowledge of Verilog/System Verilog, UVM, AXI4/AXI5 protocol, and Coherency rules in ACE and ACE5 - Experience in architecting BFMs/VIPs and handling a team of engineers - Good understanding of Power aware verification and Gate level verification - Ability to create VR as per chip requirements and develop UVM/OVM Test benches If you are passionate about Verification Engineering and have the required experience and skills, please forward your resume to jayalakshmi.r2@ust.com. (Note: No additional details of the company were included in the provided job description.),

As an experienced professional with 4 - 12 years of experience, you will be responsible for the following key aspects: - Experience in Logic design / RTL coding is a must. - Experience in SoC design and integration for complex SoCs is a must. - Experience in Verilog/System-Verilog is a must. - Experience in Multi Clock designs, Asynchronous interface is a must. - Experience in using the tools in ASIC development such as Lint and CDC. - Experience in Synthesis / Understanding of timing concepts is a plus. - Experience in ECO fixes and formal verification. - Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. - Excellent oral and written communications skills. - Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. If you are passionate about working in a dynamic environment and possess the required technical expertise, this role offers you an opportunity to showcase your skills in a challenging yet rewarding setting.,

As a RTL Design Lint CDC at Sequentia Technologies Pvt Ltd in Bengaluru, your role will involve day-to-day tasks related to RTL design, linting, and CDC methodologies. You will be responsible for ensuring the integrity of RTL designs by utilizing linting tools and conducting Clock Domain Crossing (CDC) analysis. It is essential to have proficiency in RTL design and verification, along with knowledge of industry-standard RTL coding styles and methodologies. Additionally, a strong understanding of synchronous design concepts is required for this position. Key Responsibilities: - Perform RTL design and verification tasks - Utilize linting tools for design integrity - Conduct Clock Domain Crossing (CDC) analysis - Adhere to industry-standard RTL coding styles and methodologies - Understand and implement synchronous design concepts Qualifications: - Proficiency in RTL design and verification - Experience with linting tools and Clock Domain Crossing (CDC) analysis - Knowledge of industry-standard RTL coding styles and methodologies - Strong understanding of synchronous design concepts,

As a VLSI RTL IP or Subsystem designer with 5 to 14 years of experience, you will be responsible for designing and developing CXL and DRAM controller (DDR4/5) based intellectual property. Your role will involve engaging with other architects within the IP level to drive Micro-Architectural definition and delivering quality micro-architectural level documentation. You will need to produce quality RTL on schedule by meeting PPA goals and be accountable for logic design/RTL coding, RTL integration, and timing closure of blocks. Collaboration with the verification team will be essential to ensure implementation meets architectural intent. Your hands-on experience in running quality checks such as Lint, CDC, and Constraint development will be valuable, along with a deep understanding of fundamental concepts of digital design. Key Responsibilities: - Design and develop CXL and DRAM controller based intellectual property - Engage with other architects to define Micro-Architecture - Deliver quality micro-architectural level documentation - Produce quality RTL on schedule meeting PPA goals - Responsible for logic design/RTL coding, integration, and timing closure - Collaborate with verification team to ensure implementation meets architectural intent - Conduct quality checks such as Lint, CDC, and Constraint development - Debug designs in simulation environments - Have a deep understanding of fundamental concepts of digital design Preferred Skills: - Strong Verilog/System Verilog RTL coding skills - Experience with DRAM Memory Controller design - Knowledge of DRAM standard (DDR4/5) memory - Interface/Protocol experience required: AHB/AXI, Processor local bus, Flash, SPI, UART, etc. - Experience with Xilinx/Intel FPGA Tool flow - Knowledge of PCIe/PIPE - Knowledge of projects with Microblaze, ARM cores, etc. - Appreciation for CXL Protocol Qualifications Required: - Masters degree or Bachelors degree in Electronics or Electrical Engineering - 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure (Note: Additional details about the company were not included in the provided job description.),