Rocket Chip Generator

Pure Scala Artifact Fetching

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

educational microarchitectures for risc-v isa

Implementation of some interesting ideas of deeplearning.

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Common RTL blocks used in SiFive's projects

Antmicro's fast, vendor-neutral DMA IP in Chisel

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Marginally better than redstone

Examples for creating AXI-interfaced peripherals in Chisel

HDMI core in Chisel HDL

A scala based simulator for circuits described by a LoFirrtl file