Verilog header for easier AXI interface declaration & connection

A presentation about Advanced Microcontroller Bus Architecture

Реализация AXI интерфейса на SystemVerilog

Synchronous and Asynchronous FIFO with AXI interface

RTL code for DMA controller

Knowledge hub for digital interfaces

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Formal AXI verification properties from the eXpect framework for secure SoC validation

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

AXI to Peripheral Interconnect

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

Common SystemVerilog RTL modules for RgGen

Xilinx AXI VIP example of use

Simple single-port AXI memory interface

AXI X-Bar

Network on Chip Implementation written in SytemVerilog

AMBA AXI VIP

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication