Control and status register code generator toolchain

Code generation tool for control and status registers

An open-source HDL register code generator fast enough to run in real time.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Functional Bus Description Language compiler backend for Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Functional Bus Description Language compiler front-end written in Go.

A presentation about Advanced Microcontroller Bus Architecture

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Userspace I/O library for Xilinx AXI S2MM DMA

JTAG to AXI master

Common SystemVerilog RTL modules for RgGen

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

Fol app is a hands-on full-stack learning app built with React, Node, Express & PostgreSQL. Sign up to explore real-time examples, live code demos, and practical tutorials—all freely accessible and deployed on GitHub to help you learn by doing. Perfect for beginners and curious devs!

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model