Some of small codes and implementation of modules in Computer Aided Design in VHDL by ActiveHDL

forked Digilent Demo

Repository for DSP matrix multiplier IP core and other related side projects

ADS1115 Communication with AXI interface example with zybo board

Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.

Example of transfer UDP packets from AXI DMA with SG mode.

DMA source and sink blocks for Xilinx Zynq FPGAs

Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP