A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
This repository contains a collection of small Verilog modules for various purposes.
Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.
Router 1x3 Design and Verification in Verilog
This repository consists of four projects or "labs" which were developed for the needs of the course "Digital Systems Lab". This course is part of the undergraduate studies of University of Thessally - ECE Department located in Volos, Greece.
FSM: Sequence Detector using Verilog HDL
Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.
This repository contains two Verilog modules—a 4-bit synchronous up-counter and an input-triggered finite state machine (FSM)—along with simulation testbenches. Designed to demonstrate clock-driven logic, memory retention, and real-time state transitions using edge detection and synchronous resets.
RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.
Simulation of logic circuits using Verilog, Proteus and other tools.
ALU Built with proper Datapath and Control path (FSM) to give appropriate results
Verilog Code Challenge – KVLSI Kohort 2
RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.
A collection of Verilog modules and testbenches developed for digital system design exercises, including registers, counters, state machines, and multiplexers
A reliable drone flight data recorder designed with FPGA logic to capture and store real-time trajectory (x,y,z) and attitude (Roll, Pitch, Yaw) data.
Traffic Light Controller This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring smooth vehicle movement at intersections through an efficient state-based control mechanism.
Finite State Machine (FSM) designed to handle the movements of a Land Rover based on binary inputs. The FSM utilizes D flip-flops and combinatorial logic to transition between states and produce appropriate output signals for controlling the Land Rover's movement.
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments