fsm
A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
Here are 48 public repositories matching this topic...
Final project for an advanced course in computer architecture, involving a full processor design and assembly code to run a game of Tic-Tac-Toe
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Nov 1, 2017 - Verilog
Complex Adder with Seven Segment Display
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Apr 24, 2018 - Verilog
verilog practice, counter, fsm, traffic light
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Aug 1, 2018 - Verilog
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
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Dec 9, 2018 - Verilog
Desenvolvimento de uma aplicação sobre sobre Máquina de Estados Finita, desenvolvida nos dois modelos de comunicação: Síncrona e Assíncrona, para a disciplina de Arquitetura de Computadores II Unisinos-2019.
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Mar 28, 2019 - Verilog
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
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May 10, 2019 - Verilog
Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.
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Dec 8, 2019 - Verilog
Verilog Programs
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Apr 16, 2021 - Verilog
These are all implemented using Verilog for my Logic Design Laboratory Class （邏輯設計實驗）, and I am using a Basys3 FPGA Board.
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May 1, 2021 - Verilog
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Aug 20, 2022 - Verilog
Finite State Machine (FSM) designed to handle the movements of a Land Rover based on binary inputs. The FSM utilizes D flip-flops and combinatorial logic to transition between states and produce appropriate output signals for controlling the Land Rover's movement.
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Jul 13, 2023 - Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
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Sep 15, 2023 - Verilog
The project below orients the likes of Verilog, Intel Quartus Prime, and DE1_SoC boards to compute a combination lock through Moore FSM applications!
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Jan 12, 2024 - Verilog
SerDes RTL design, verification using UVM and Physical design.
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May 26, 2024 - Verilog
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
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May 28, 2024 - Verilog
FSM: Sequence Detector using Verilog HDL
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Jul 12, 2024 - Verilog
RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.
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Aug 3, 2024 - Verilog
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