Automatic irrigation controller in VHDL with ASM charts, testbenches, and full Quartus + ModelSim support.

This project implements a Finite State Machine (FSM) for processing sequences stored in RAM, in VHDL

FSM-based SPI Master implementation in VHDL with simulation and docs

Terminal access controller

Course assignments of COL215:- Digital Logic and System Design course at IIT Delhi under Professor Preeti Ranjan Panda

CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .

VHDL-based digital logic project from Politecnico di Milano, featuring a convolutional encoder for telecommunications. Implements a finite state machine (FSM) to process sequences from memory, doubling the number of output words.

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.

In a team of 4 we wanted create a replication of the popular Flappy Bird game, using digital logic and design, controlled by a PS/2 mouse and displayed on a VGA screen.

Computer Architecture Project using VHDL

VHDL module for histogram equalization, aiming to enhance image contrast using digital circuit design techniques in VHDL

A team-project about a fem vending-machine I had in 2nd year of uni

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.

Final exam of "Logical Networks" - Polimi Computer Science Engineering - A.Y. 2022-2023

Final project of Logical Networks course - Politecnico di Milano 2022/23

This repository contains my custom finite state machine algorithms and their corresponding testbenches, generated using TerosHDL, for robust validation.

Design in VHDL of an hardware component for the Logic Circuit Design course @ PoliMi

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.