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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 66 public repositories matching this topic...

slaclab / surf

A huge VHDL library for FPGA and digital ASIC development

python asic fpga firmware vhdl hdl

Updated Nov 12, 2025
VHDL

icarogabryel / vhdl-fine-multiplier

A multiplier that uses the the radix-4 Booth's algorithm and Wallace Tree implementation in VHDL

hardware hardware-designs computer-architecture hdl computer-organization integrated-circuits multiplier booths-algorithm

Updated Nov 12, 2025
VHDL

neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv smp multi-core rtos hdl soc risc-v soft-core system-on-chip rv32 asip neorv32 on-chip-debbuger

Updated Nov 7, 2025
VHDL

AlexNoodle0127 / Intel4004Clone

This file contains a work-in-progress Intel4004 Clones as well as a Readme discussing my post-Von Neumann idea of what computing can be.

vhdl hdl symbolic-computation cpu-design intel4004 meta-architecture post-von-neumann

Updated Nov 5, 2025
VHDL

PeterAyad / Verilog-VHDL-Examples

The Verilog And VHDL Examples I Made When I Was An Undergraduate Student

vhdl verilog hdl hardware-description-language

Updated Oct 26, 2025
VHDL

VHDL / PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

library asic collection fpga vhdl diamond verification xilinx synthesis vivado altera hdl ghdl quartus nvc ipcore

Updated Oct 14, 2025
VHDL

Choaib-ELMADI / getting-started-with-vhdl

Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.

design fpga digital vhdl circuit hdl fpga-soc fpga-board vhdl-code vhdl-examples fpga-programming

Updated Oct 12, 2025
VHDL

stnolting / neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl chaos rtl rng random-number-generators hdl key-generator trng entropy-source ring-oscillator asic-design neorv32

Updated Sep 11, 2025
VHDL

nselvara / HDL-Core-Library

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl2008 vhdl-testbench eda-playground

Updated Sep 25, 2025
VHDL

nselvara / VHDL-Utils

A VHDL code base that contains Utility Packages for both HDL and Testbenches

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl-testbench eda-playground

Updated Aug 19, 2025
VHDL

sampai97 / Modular-FFT-radix-2

VHDL modular Fast Fourier Transform based on Cooley-Tukey algorithm

vhdl fft cooley-tukey-fft hdl cooley tukey fourier-transform fastfouriertransform vhdl-code radix2 vhdl-project

Updated Aug 11, 2025
VHDL

franos-cm / dilithium-comparison

Comparison between two RTL designs that fully implement the CRYSTALS-Dilithium algorithm

hdl hardware-acceleration dilithium crystals-dilithium

Updated Aug 7, 2025
VHDL

vankxr / icyradio

Over-engineered SDR development board

Updated Aug 3, 2025
VHDL

LuisMLopez-dev / Double-Dabble-Algorithm

This is a VHDL program for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.

programming fpga vhdl hdl xilinx-vivado nexys4ddr digital-circuit-design

Updated Jul 28, 2025
VHDL

Santana-DS / OAC_GRUPO-B3

OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)

cpu vhdl riscv hdl modelsim risc-v unb oac quartus pipeline-cpu harware multi-cycle-cpu uni-cycle-cpu

Updated Jul 14, 2025
VHDL

emeralddd123 / Parking-Assistant-FPGA

Parking Assistant Implemented with VHDL on Max10 DE Lite Board

fpga vhdl hdl parking-assistant

Updated Jun 2, 2025
VHDL

dotrocks / dsd_project_2_security_system

AGU EEE DSD Capsule Project - Home Security System

security fpga vhdl hdl capsule agu

Updated May 20, 2025
VHDL

davidel / pyxhdl

Python Frontend For VHDL And Verilog

python vhdl verilog systemverilog hdl

Updated May 1, 2025
VHDL

sbaldzenka / uart_core

UART IP-core for FPGA.

fpga vhdl diamond uart hdl modelsim questasim ip-core lattice-fpga machxo3

Updated Feb 14, 2025
VHDL

MohammedS2lah / Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

vhdl hardware-designs hdl vhdl-modules hardware-description-language vhdl-code vhdl-examples vhdl-testbench hardware-design vhdl-language

Updated Jan 24, 2025
VHDL

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