Test suite designed to check compliance with the SystemVerilog standard.
-
Updated
Nov 14, 2025 - SystemVerilog
#
hdl
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 105 public repositories matching this topic...
Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).
llvm verilog systemverilog hardware-designs hdl verilog-hdl hierachical verilog-code hierachical-structure llm-based hivegen hierarchical-hardware-design demo-paper-implementation paper-demo hivegen-demo
-
Updated
Nov 8, 2025 - SystemVerilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.
testing design asic fpga hardware verification rtl systemverilog hardware-designs hdl modelsim questasim uvm testbench systemverilog-hdl rtl-design uvm-verification
-
Updated
Nov 5, 2025 - SystemVerilog
SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.
python machine-learning fpga neural-network tensorflow rtl neural-networks verilog perceptron systemverilog fixed-point hdl sigmoid sigmoid-function relu ai-hardware
-
Updated
Oct 27, 2025 - SystemVerilog
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core
-
Updated
Oct 19, 2025 - SystemVerilog
SystemVerilog Logger
-
Updated
Sep 30, 2025 - SystemVerilog
Designed and implemented a 5-stage pipelined RISCV processor supporting data hazard resolution via stalling, forwarding, and pipeline flushing. Achieved full functional and performance compliance with RV32I subset (ADD, ADDI, SUB, LW, SLT, JAL)
-
Updated
Sep 15, 2025 - SystemVerilog
5-Stage RISC-V Processor with Verification Environment
-
Updated
Sep 11, 2025 - SystemVerilog
-
Updated
Sep 3, 2025 - SystemVerilog
4×4 7-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.
fpga rtl matrix-multiplication verilog python-driver systemverilog hdl uvm uvc 8bit digital-design basys3 hardware-verification hardware-accelerator systolic-array
-
Updated
Sep 2, 2025 - SystemVerilog
Pipelined IEEE-754 single-precision floating-point multiplier in SystemVerilog with full verification.
simulation multiplication verification rtl floating-point ieee-754 pipelining computer-architecture hdl questasim system-verilog digital-design sva intel-fpga hardware-design
-
Updated
Aug 17, 2025 - SystemVerilog
A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.
open-source fpga rtl loopback uart altera digital-logic systemverilog hdl serial-communication cyclone-v educational-project intel-quartus hardware-design
-
Updated
Aug 11, 2025 - SystemVerilog
View my answers to some HDL questions listed for practice on chipdev. I prefer it to HDLBits, but I might add a couple things from there ;)
-
Updated
Aug 8, 2025 - SystemVerilog
Ultra-precise human reaction meter
-
Updated
Jul 31, 2025 - SystemVerilog
- Followers
- 492 followers
- Website
- github.com/topics/verilog
- Wikipedia
- Wikipedia