Boolean expression simplifier and visualizer

Design of mips pipeline microprocessor architecture using system verilog

This software is designed to help Computer/Electric Hardware Engineers design an efficient digital logic circuit with best optimisation for lowest cost and power consumption to implement any function.

ELVE : ELVE Logic Visualization Engine

All the homeworks, testers and projects done at METU-CENG

VHDL Samples

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

Programming Assignments during freshman year (201309 - 201406), NTUEE

COEN 921C Introduction to Logic Design, Carl Fussell, Santa Clara University

🚀🏞️ A complete village Scenarry with C graphics. 🏕️🏝️

A place for my asynchronous logic code

University of Marmara, CSE3015 2018 Fall Project

Game built using Logic and Verilog on a BASYS2 board.

Logic Design Laboratory

A Logic Gate Simulator Using Artificial Deep Neural Networks

🚀 Visit this shopping cart site: 💻https://priontoabdullah.github.io/shopping-cart-js/index.html

Two's complement two bit multiplier developed in Proteus

A SimCirJS fork with enhanced functionalities

Basic Operations of a Processor in Xilinx