risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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Example RISC-V implementation that tracks objects. Implemented on a Microsemi SmartFusion2.
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Jan 28, 2018 - Verilog
RISC-V 32-bit processor that runs a 2.5D maze game; Built for CPTR380 Winter of 2018 at Walla Walla University
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Nov 28, 2018 - Verilog
Basic RISC-V Test SoC
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Apr 7, 2019 - Verilog
A processor my partner (Nathan Ackermann) and I created in verilog for our computer organization class. It is compatible with most of the RISC-V base ISA.
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May 1, 2019 - Verilog
XCrypto: a cryptographic ISE for RISC-V
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Jun 27, 2019 - Verilog
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino
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Dec 11, 2019 - Verilog
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