🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A 32 bit RISC-V RV32IM CPU described in Verilog HDL.

16 bit RISC-V proof of concept

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

⚡ 32-bit, single-cycle RISC-V (RV32I) processor implemented entirely in VHDL-2008. It includes a complete toolchain for compiling and simulating C and Assembly programs, making it an ideal educational project for studying computer architecture.

Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.

OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)

This project offers a Risc-V implementation that is able to execute multiple fine grained threads in a single CPU

See beyond reality: Image super-resolution carved into silicon (FPGA Ignite 2024)

Risc-V pipelined CPU and SoC written in SystemVerilog

Design and implementation of a 32-bit RISC-V processor supporting the RV32IM instruction set, developed as part of the Advanced Computer Architecture course (CO502)

NEORV32 RISC-V Core: Formal Verification Using SST & PC-Based Checking

Development of a Risc-V microprocessor capable of processing basic assembly instructions, as well as implementing some AVX instructions and enabling the processor to support them.

APB Interfacing logic for Propell

Course assignments of COL216:- Computer Architecture course at IIT Delhi under Professor Kolin Paul

RISC-V RV32I, 5 stages pipelined - FPGA softcore target

Une implémentation du processeur simplifié RISC-V sans pipeline dans le livre de Hennessy / Patterson