Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
📦 The Largest Collection of Pre-Compiled Cargo/Rust Static Binaries for Soar: The Modern, Bloat-Free Distro-Independent Package Manager
VSCode Plugins for RISC-V Developers. A part of RuyiSDK.
Immutable.Friendly.Secure — Reliable embedded Linux for any device
RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/
Open-source high-performance RISC-V processor
Verilog implementations of single-cycle, multi-cycle and pipelined RISC-V CPUs.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Example projects for the IAR RISC-V Evaluation Board
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
Implementing core machine learning algorithms from scratch in RISC-V assembly to build an intuition for how they work behind the scenes.
Linux RISC-V virtual machine, powered by the Cartesi Machine emulator, running in the browser via WebAssembly
Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax
Pico Pico - Embedded Programming with Raspberry Pi Pico 2 and Rust
Bao, a Lightweight Static Partitioning Hypervisor
RISC-V Directed Test Framework and Compliance Suite, RiESCUE
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
A secure embedded operating system for microcontrollers