Bare-metal programming on BL602 single-core RISC-V SiFive E24 (Pinecone BL602 Evaluation Board) without using Bouffalo Lab's SDK

An ambitious attempt at documenting the bl602 better then the manufacturers themselves did through practical little code examples

Freedom U Software Development Kit (FUSDK)

SiFive OpenEmbedded / Yocto BSP Layer

HiFive01-RevB is the SiFive's RISC-V based board

RISC-V Debugger

Stuff related to RISC-V

Bare metal programming on the RED-V Thing Plus board (SiFive RISC-V FE310 SoC)

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

Development of some Risc-V drivers for the FE310-G002 (SoC)

SiFive: development platform for PlatformIO

A custom development board for the SiFive FE310, a RISC-V microcontroller.

SiFive's Freedom e300 for the DECA Max10 FPGA

RISC-V Engine Emulator

RISCV port of the Slackware distribution

Read and write a memory-mapped SiFive system-on-chip UART

OSdev exploration

Reverse engineer of the hifive1 rev b bootloader since the source has not been released