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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

SystemVerilog 433 322 Built by @davidharrishmc @rosethompson @jordancarlin @BBracker @kparry4 1 star this week
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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,402 319 Built by @andreaskurth @thommythomaso @micprog @suehtamacv @zarubaf 2 stars this week
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openhwgroup / cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SystemVerilog 540 145 Built by @michael-platzer @zarubaf @lucabertaccini @davideschiavone @stmach 3 stars this week