{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T21:57:57Z","timestamp":1755035877935},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1109\/dft.2010.22","type":"proceedings-article","created":{"date-parts":[[2010,11,19]],"date-time":"2010-11-19T16:32:37Z","timestamp":1290184357000},"page":"129-135","source":"Crossref","is-referenced-by-count":18,"title":["Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory"],"prefix":"10.1109","author":[{"given":"Ming","family":"Zhu","sequence":"first","affiliation":[]},{"given":"Liyi","family":"Xiao","sequence":"additional","affiliation":[]},{"given":"Shuhao","family":"Li","sequence":"additional","affiliation":[]},{"given":"Yanjing","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.59"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455247"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.29"},{"key":"ref13","first-page":"1","article-title":"Matrix codes for reliable and cost efficient memory chips","author":"argyrides","year":"2009","journal-title":"IEEE Trans VLSI Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860675"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.897066"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19952162"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2008.2007647"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269335"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821938"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681832"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.2"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/944027.944038"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.892119"}],"event":{"name":"2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)","start":{"date-parts":[[2010,10,6]]},"location":"Kyoto, Japan","end":{"date-parts":[[2010,10,8]]}},"container-title":["2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5629473\/5634869\/05634874.pdf?arnumber=5634874","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T02:58:50Z","timestamp":1490065130000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5634874\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dft.2010.22","relation":{},"subject":[],"published":{"date-parts":[[2010,10]]}}}