{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T21:52:07Z","timestamp":1777153927500,"version":"3.51.4"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/hpca.2011.5749752","type":"proceedings-article","created":{"date-parts":[[2011,4,18]],"date-time":"2011-04-18T13:49:44Z","timestamp":1303134584000},"page":"466-477","source":"Crossref","is-referenced-by-count":101,"title":["FREE-p: Protecting non-volatile memory against both hard and soft errors"],"prefix":"10.1109","author":[{"given":"Doe Hyun","family":"Yoon","sequence":"first","affiliation":[]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[]},{"given":"Jichuan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Parthasarathy","family":"Ranganathan","sequence":"additional","affiliation":[]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736064"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852666"},{"key":"ref31","article-title":"A low power phase-change random access memory using a data-comparison write scheme","year":"2007","journal-title":"ISCAS"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref35","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360134","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"2000","journal-title":"Micro"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669116"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"ref11","article-title":"Energy-and endurance-aware design of phase change memory caches","author":"joo","year":"2010","journal-title":"DATE"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588577"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref14","article-title":"NAND Flash Translation Layer (NFTL) 4.5.0 User Guide","year":"2010"},{"key":"ref15","article-title":"System and method for controlling application of an error correction code","author":"nerl","year":"2007"},{"key":"ref16","article-title":"128-Mbit Parallel Phase Change Memory","year":"2010"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2004.836724"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"ref3","article-title":"BIOS and kernel developer's guide for AMD NPT family 0Fh processors","year":"2007"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1116\/1.3301579"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0307"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.82"},{"key":"ref1","article-title":"ITRS 2008 update","year":"2008","journal-title":"Tech report Int'l Tech Roadmap for Semiconductors"},{"key":"ref20","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341526"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816014"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555372"},{"key":"ref26","article-title":"The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories","author":"strukov","year":"2009","journal-title":"Asilomar Conf"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.46"}],"event":{"name":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)","location":"San Antonio, TX, USA","start":{"date-parts":[[2011,2,12]]},"end":{"date-parts":[[2011,2,16]]}},"container-title":["2011 IEEE 17th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5743111\/5749710\/05749752.pdf?arnumber=5749752","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,6]],"date-time":"2024-04-06T06:21:00Z","timestamp":1712384460000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5749752\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/hpca.2011.5749752","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}