{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T06:58:11Z","timestamp":1725519491960},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/iccd.2016.7753255","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T16:40:00Z","timestamp":1480005600000},"page":"9-16","source":"Crossref","is-referenced-by-count":0,"title":["An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor"],"prefix":"10.1109","author":[{"given":"Keni","family":"Qiu","sequence":"first","affiliation":[]},{"given":"Yuanhui","family":"Ni","sequence":"additional","affiliation":[]},{"given":"Weigong","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Jing","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Xiaoqiang","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[]},{"given":"Tao","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.53"},{"journal-title":"The Cell Project","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228480"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2006.9"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765953"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944891"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155677"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903010"},{"journal-title":"NIRGAM","year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2009.22"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-009-9295-3"},{"key":"ref6","first-page":"1","article-title":"Defensive loop tiling for shared cache","author":"bao","year":"2013","journal-title":"IEEE\/ACM International Symposium on Code Generation and Optimization"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597922"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542286"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086716"},{"key":"ref2","first-page":"49","article-title":"Mul-tiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies","author":"issenin","year":"2006","journal-title":"Proceedings of the 43rd Annual Design Automation Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810095"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854351"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1067915.1067922"}],"event":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","start":{"date-parts":[[2016,10,2]]},"location":"Scottsdale, AZ, USA","end":{"date-parts":[[2016,10,5]]}},"container-title":["2016 IEEE 34th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7742853\/7753252\/07753255.pdf?arnumber=7753255","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,21]],"date-time":"2016-12-21T17:14:21Z","timestamp":1482340461000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7753255\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iccd.2016.7753255","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}