{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:27Z","timestamp":1740133287574,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee, Hong Kong","doi-asserted-by":"publisher","award":["CUHK14209214"],"award-info":[{"award-number":["CUHK14209214"]}],"id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2461463","type":"journal-article","created":{"date-parts":[[2015,8,18]],"date-time":"2015-08-18T18:39:08Z","timestamp":1439923148000},"page":"1319-1332","source":"Crossref","is-referenced-by-count":2,"title":["Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2659-0040","authenticated-orcid":false,"given":"Jian","family":"Kuang","sequence":"first","affiliation":[]},{"given":"Wing-Kai","family":"Chow","sequence":"additional","affiliation":[]},{"given":"Evangeline F. Y.","family":"Young","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691116"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228468"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429408"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691142"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2401571"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001341"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717770"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1117\/12.964381"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429396"},{"key":"ref19","first-page":"48","article-title":"An efficient and effective detailed placement algorithm","author":"pan","year":"2005","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105297"},{"key":"ref3","first-page":"81660x-1","article-title":"Double patterning from design enablement to verification","volume":"8166","author":"abercrombie","year":"2011","journal-title":"Proc SPIE"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228579"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"433","DOI":"10.1109\/TCAD.2014.2387840","article-title":"Layout decomposition for triple patterning lithography","volume":"34","author":"yu","year":"2015","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488818"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2288678"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681616"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691114"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001340"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560523"},{"journal-title":"NanGate FreePDK45 Generic Open Cell Library","year":"2015","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.760005"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488922"},{"journal-title":"ISPD 2014 Detailed Routing-Driven Placement Contest","year":"2015","key":"ref23"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429539"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7208898.pdf?arnumber=7208898","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:43Z","timestamp":1633919683000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208898\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":25,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2461463","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}