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In applications where Euclidean precision is not essential the L<jats:sub>\u221e<\/jats:sub> Voronoi diagram can provide a better alternative. Using the L<jats:sub>\u221e<\/jats:sub> Voronoi diagram of polygons we address the problem of calculating the critical area for shorts in a VLSI layout. The critical area computation is the main computational bottleneck in VLSI yield prediction. <\/jats:p>","DOI":"10.1142\/s0218195901000626","type":"journal-article","created":{"date-parts":[[2003,5,7]],"date-time":"2003-05-07T08:18:55Z","timestamp":1052295535000},"page":"503-528","source":"Crossref","is-referenced-by-count":43,"title":["THE L<sub>\u221e<\/sub> VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS"],"prefix":"10.1142","volume":"11","author":[{"given":"EVANTHA","family":"PAPADOPOULOU","sequence":"first","affiliation":[{"name":"IBM TJ Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D. 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