{"id":"https://openalex.org/W2137589342","doi":"https://doi.org/10.1109/mdt.2004.1261846","title":"An integrated environment for technology closure of deep-submicron IC designs","display_name":"An integrated environment for technology closure of deep-submicron IC designs","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2137589342","doi":"https://doi.org/10.1109/mdt.2004.1261846","mag":"2137589342"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2004.1261846","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2004.1261846","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090180563","display_name":"Louise Trevillyan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"L. Trevillyan","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM Thomas J. Watson Res. Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM Thomas J. Watson Res. Center, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063522852","display_name":"David S. Kung","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Kung","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM Thomas J. Watson Res. Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM Thomas J. Watson Res. Center, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045722906","display_name":"Ruchir Puri","orcid":"https://orcid.org/0009-0006-8803-7079"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Puri","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM Thomas J. Watson Res. Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM Thomas J. Watson Res. Center, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102913365","display_name":"Lakshmi Reddy","orcid":"https://orcid.org/0000-0002-0482-1645"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L.N. Reddy","raw_affiliation_strings":["Microelectronics Division, IBM, USA","IBM Microelectronics Division#TAB#"],"affiliations":[{"raw_affiliation_string":"Microelectronics Division, IBM, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Microelectronics Division#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039171865","display_name":"Michael A. Kazda","orcid":"https://orcid.org/0000-0001-7890-8463"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.A. Kazda","raw_affiliation_strings":["Microelectronics Division, IBM, USA","IBM Microelectronics Division#TAB#"],"affiliations":[{"raw_affiliation_string":"Microelectronics Division, IBM, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Microelectronics Division#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5090180563"],"corresponding_institution_ids":["https://openalex.org/I4210114115"],"apc_list":null,"apc_paid":null,"fwci":7.2414,"has_fulltext":false,"cited_by_count":84,"citation_normalized_percentile":{"value":0.97394691,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"21","issue":"1","first_page":"14","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interoperability","display_name":"Interoperability","score":0.7136610150337219},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6508563756942749},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5909873843193054},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5780767202377319},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5725426077842712},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5633913278579712},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5618821382522583},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5578335523605347},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5542829036712646},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5408395528793335},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5230827331542969},{"id":"https://openalex.org/keywords/closure","display_name":"Closure (psychology)","score":0.49575576186180115},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4760831892490387},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4698321521282196},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.4549935758113861},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42561736702919006},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40758854150772095},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.25923866033554077},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12235832214355469},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11135846376419067},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10272696614265442}],"concepts":[{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.7136610150337219},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6508563756942749},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5909873843193054},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5780767202377319},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5725426077842712},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5633913278579712},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5618821382522583},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5578335523605347},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5542829036712646},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5408395528793335},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5230827331542969},{"id":"https://openalex.org/C146834321","wikidata":"https://www.wikidata.org/wiki/Q2979672","display_name":"Closure (psychology)","level":2,"score":0.49575576186180115},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4760831892490387},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4698321521282196},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.4549935758113861},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42561736702919006},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40758854150772095},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25923866033554077},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12235832214355469},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11135846376419067},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10272696614265442},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2004.1261846","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2004.1261846","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1483017465","https://openalex.org/W1552744738","https://openalex.org/W1976809982","https://openalex.org/W2097806352","https://openalex.org/W2100525812","https://openalex.org/W2108665876","https://openalex.org/W2109846948","https://openalex.org/W2139429728","https://openalex.org/W4238999275","https://openalex.org/W4245023281","https://openalex.org/W4253824801"],"related_works":["https://openalex.org/W2146286671","https://openalex.org/W2743305891","https://openalex.org/W2130825721","https://openalex.org/W3205162826","https://openalex.org/W2121036163","https://openalex.org/W4321510758","https://openalex.org/W2093513607","https://openalex.org/W2110346573","https://openalex.org/W3112090072","https://openalex.org/W2118796996"],"abstract_inverted_index":{"With":[0],"larger":[1],"chip":[2],"images":[3],"and":[4,30],"increasingly":[5],"aggressive":[6],"technologies,":[7],"key":[8],"design":[9],"processes":[10,22],"must":[11],"interoperate,":[12],"PDS,":[13],"a":[14,34],"physical-synthesis":[15],"system,":[16],"accomplishes":[17],"technology":[18],"closure":[19],"through":[20],"interacting":[21],"of":[23],"logic":[24],"optimization,":[25],"placement,":[26],"timing,":[27],"clock":[28],"insertion,":[29],"routing,":[31],"all":[32],"using":[33],"common":[35],"infrastructure":[36],"with":[37],"robust":[38],"variable-accuracy":[39],"analysis":[40],"abstractions.":[41]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":13}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}