Bruno Bodin's homepage

Faust to FPGA

This project integrates a Synchronous Dataflow backend into the Faust language toolchain, enabling static analysis and synthesis of audio applications onto FPGA hardware. Read more...

In the context of Jaime Koh PhD researchKoh2022, we integrated our Synchronous Dataflow backend into the Faust language toolchain. This enable the use of any Faust application in the context of dataflow analysis research compatible with the SDF3 format. Read more...

K-Periodic Scheduling for Throughput-Buffering Trade-Off Exploration of CSDF

The design of time-critical embedded systems often requires static models of computation such as cyclo-static dataflow. These models enable performance guarantees, execution correctness, and optimized memory usage. Nonetheless, determining optimal buffer... Read more...

Static Performance Analysis of Faust Programs Using Dataflow Modelling

The processing capabilities of modern System-on-Chips allow artists to push the boundaries of digital art by enabling the implementation of complex real-time signal processing applications. The Faust framework has simplified the process of implementing signal... Read more...

Spectrum: Software-defined Architecture for 5G

SPECTRUM is a software-defined array-based many-core architecture designed for predictable real-time processing in 5G baseband systems. It integrates lightweight hardware with a compiler flow based on SDF models.

ASCENT: Communication Scheduling for SDF on Bufferless Software-defined NoC

Bufferless software-defined Network-on-Chip (NoC) is a promising alternative to conventional dynamic routing as it offers predictable data movement with real-time guarantees. Existing Time-Division Multiplexing (TDM)-based mechanisms for predictability assume... Read more...

Time-predictable software-defined architecture with sdf-based compiler flow for 5G baseband processing

We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing... Read more...

Dataset Generation and Benchmarking of SLAM Algorithms for Robotics and VR/AR

Synthetic datasets have gained an enormous amount of popularity in the computer vision community, from training and evaluation of Deep Learning-based methods to benchmarking Simultaneous Localization and Mapping (SLAM). Read more...

The PAMELA project

Designing computer systems for the next generation many-core applications is an extremely challenging problem. This programme brought together application developers, system software researchers and computer architects. Read more...

SLAMBench2

SLAMBench is a SLAM performance benchmark that combines a framework for quantifying quality-of-result with instrumentation of accuracy, execution time, memory usage and energy consumption. It also include a graphical interface to visualize these information.... Read more...

SimBench: A Portable Benchmarking Methodology for Full-System Simulators

In this paper we present SimBench, an extensive suite of targeted micro-benchmarks designed to run bare-metal on a full-system simulator. SimBench exercises dynamic-binary translation (DBT) performance, interrupt and exception handling, memory access... Read more...

Diplomat: Mapping of Multi-kernel Applications Using Static Dataflow Abstraction

We propose a novel approach to heterogeneous embedded systems programmability using a task-graph based framework called Diplomat. Diplomat is a performance domain-specific language for task-graphs that exploits the potential of static dataflow modeling and... Read more...

Dataflow compilation for the Kalray MPPA-256

The Kalray MPPA-256 processor integrates 288 cores. Its SDK includes a C-based dataflow language whose compiler automates the distributed execution of tasks across the processing, memory, communication and synchronization resources of the architecture. Read more...

AccessCore (Sigma-C)

AccessCore is the MPPA Kalray toolchain, with Sigma-C its dataflow language. During my PhD I integrated the buffersizing strategy developed by Mohamed Benazouz and Alix-Munier as well as a novel liveness evaluation method for CSDFGBenazouz2013. Read more...

Kiter

Given a specific dataflow model, the Kiter tool is able to compute the maximum throughput of the application modeled by this dataflow. Kiter is based on a workBodin2016b which outperforms the state of the art. Read more...

Fast and efficient dataflow graph generation

This paper presents a new graph generator for Phased Computation Graphs (PCG), which augment Cyclo-Static Dataflow Graphs with both initial phases and thresholds. A sufficient condition of liveness is first extended to the PCG model. The determination of... Read more...

Hi. I'm Bruno Bodin.