default search action
5th MEMOCODE 2007: Nice, France
- 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France. IEEE Computer Society 2007, ISBN 1-4244-1050-9
- Ivan Radojevic, Zoran A. Salcic
, Partha S. Roop:
McCharts and Multiclock FSMs for modeling large scale systems. 3-12 - Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalkar, Luca P. Carloni:
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design. 13-22 - Xavier Leroy:
Formal verification of an optimizing compiler. 25 - Yi Lv, Huimin Lin, Hong Pan:
Computing Invariants for Parameter Abstraction. 29-38 - Rathijit Sen, Y. N. Srikant:
Executable Analysis using Abstract Interpretation with Circular Linear Progressions. 39-48 - Nirav Dave, Arvind, Michael Pellauer:
Scheduling as Rule Composition. 51-60 - Deepak Mathaikutty, Sandeep K. Shukla:
Type Inference for IP Composition. 61-70 - Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks:
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. 71-80 - Edgar G. Daylight, Sandeep K. Shukla:
Local Causal Reasoning of a Safety-Critical Subway System. 83-84 - Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler:
Multi-Level Assertion-Based Design. 85-86 - Youngseok Oh, Danhyung Lee, Sungwon Kang, Jihyun Lee:
Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded Systems. 87-88 - Forrest Brewer
MEMOCODE 2007 Co-Design Contest. 91-94 - Eric Simpson, Pengyuan Yu, Patrick Schaumont
VT Matrix Multiply Design for MEMOCODE '07. 95-96 - Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan:
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. 97-100 - Bernhard Niemann, Christian Haubelt
Towards a Unified Execution Model for Transactions in TLM. 103-112 - Nicola Bombieri
Towards Equivalence Checking Between TLM and RTL Models. 113-122 - Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik
Verification Driven Formal Architecture and Microarchitecture Modeling. 123-132 - Bertrand Meyer:
Proving What Programs Do Not. 135 - Bart D. Theelen, Oana Florescu, Marc Geilen
Software/Hardware Engineering with the Parallel Object-Oriented Specification Language. 139-148 - Wu Jigang, Thambipillai Srikanthan, Guang Chen:
One-dimensional Search Algorithms for Hardware/Software Partitioning. 149-158 - Proshanta Saha, Tarek A. El-Ghazawi:
A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems. 159-168 - Geoffrey M. Brown, Lee Pike:
Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols. 171-180 - Stephan Eggersglüß, Görschwin Fey
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. 181-187 - Hana Chockler, Ofer Strichman
Easier and More Informative Vacuity Checks. 189-198 - Byron Cook:
Bringing Hardware and Software Closer Together with Termination Analysis. 201
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-27 21:13 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: